公开(公告)号：GB2573711A

公开(公告)日：2019-11-13

申请号：GB201911360

申请日：2018-02-17

Applicant: IBM

Inventor： SANJAY MEHTA ,  BALASUBRAMANIAN PRANATHARTHIHARAN ,  ZHENXING BI ,  THAMARAI DEVARAJAN ,  MUTHUMANICKAM SANKARAPANDIAN

IPC: H01L21/28

Abstract: A vertical transport fin field effect transistor (VT FinFET), including one or more vertical fins on a surface of a substrate, an L-shaped or U-shaped spacer trough on the substrate adjacent to at least one of the one or more vertical fins, and a gate dielectric layer on the sidewalls of the at least one of the one or more vertical fins and the L-shaped or U-shaped spacer trough.

公开(公告)号：GB2575933B

公开(公告)日：2021-09-29

申请号：GB201915589

申请日：2018-04-13

Applicant: IBM

Inventor： RUQIANG BAO ,  CHOONGHYUN LEE ,  ZHENG XU ,  ZHENXING BI

IPC: H01L21/8238 ,  H01L21/336 ,  H01L27/092 ,  H01L29/08 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

Abstract: Integrated chips include a first semiconductor device and a second semiconductor device. The first semiconductor device includes a semiconductor channel, a first-type work function layer formed from a first material on the semiconductor channel, and a second-type work function layer formed from a second material on the first-type work function later layer. The second semiconductor device includes a semiconductor channel, a second-type work function layer formed the second material on the semiconductor channel, and a thickness matching layer formed on the second-type work function layer of the second semiconductor device, the thickness matching layer having a thickness roughly equal to a thickness of the first-type work function layer.

公开(公告)号：GB2573711B

公开(公告)日：2021-09-29

申请号：GB201911360

申请日：2018-02-17

Applicant: IBM

Inventor： SANJAY MEHTA ,  BALASUBRAMANIAN PRANATHARTHIHARAN ,  ZHENXING BI ,  THAMARAI DEVARAJAN ,  MUTHUMANICKAM SANKARAPANDIAN

IPC: H01L21/28

Abstract: A vertical transport fin field effect transistor (VT FinFET), including one or more vertical fins on a surface of a substrate, an L-shaped or U-shaped spacer trough on the substrate adjacent to at least one of the one or more vertical fins, and a gate dielectric layer on the sidewalls of the at least one of the one or more vertical fins and the L-shaped or U-shaped spacer trough.

公开(公告)号：GB2575933A

公开(公告)日：2020-01-29

申请号：GB201915589

申请日：2018-04-13

Applicant: IBM

Inventor： RUQIANG BAO ,  CHOONGHYUN LEE ,  ZHENG XU ,  ZHENXING BI

IPC: H01L21/336

Abstract: Semiconductor devices and methods of forming the same include forming vertical semiconductor channels on a bottom source/drain layer in a first-type region and a second-type region. A gate dielectric layer is formed on sidewalls of the vertical semiconductor channels. A first-type work function layer is formed in the first-type region. A second-type work function layer is formed in both the first-type region and the second-type region. A thickness matching layer is formed in the second-type region such that a stack of layers in the first-type region has a same thickness as a stack of layers in the second-type region. Top source/drain regions are formed on a top portion of the vertical channels.