公开(公告)号：GB2579487B

公开(公告)日：2021-12-15

申请号：GB202001682

申请日：2018-07-16

Applicant: IBM ,  GLOBALFOUNDRIES INC ,  SAMSUNG ELECTRONICS CO LTD

Inventor： SU CHEN FAN ,  BALASUBRAMANIAN PRANATHARTHIHARAN ,  ANDREW GREENE ,  RUILONG XIE ,  MARK VICTOR RAYMOND ,  SEAN LIAN

IPC: H01L21/768 ,  H01L21/8238

Abstract: Techniques for forming self-aligned contacts by forming gate sidewall spacers and gates before forming the contacts are provided. In one aspect, a method of forming self-aligned contacts includes the steps of: forming multiple gate sidewall spacers on a substrate; burying the gate sidewall spacers in a dielectric; forming gate trenches by selectively removing the dielectric from regions between the gate sidewall spacers in which gates will be formed; forming the gates in the gate trenches; forming contact trenches by selectively removing the dielectric from regions between the gate sidewall spacers in which the self-aligned contacts will be formed; and forming the self-aligned contacts in the contact trenches. A device structure having self-aligned contacts is also provided.

公开(公告)号：GB2573711A

公开(公告)日：2019-11-13

申请号：GB201911360

申请日：2018-02-17

Applicant: IBM

Inventor： SANJAY MEHTA ,  BALASUBRAMANIAN PRANATHARTHIHARAN ,  ZHENXING BI ,  THAMARAI DEVARAJAN ,  MUTHUMANICKAM SANKARAPANDIAN

IPC: H01L21/28

Abstract: A vertical transport fin field effect transistor (VT FinFET), including one or more vertical fins on a surface of a substrate, an L-shaped or U-shaped spacer trough on the substrate adjacent to at least one of the one or more vertical fins, and a gate dielectric layer on the sidewalls of the at least one of the one or more vertical fins and the L-shaped or U-shaped spacer trough.

公开(公告)号：GB2627627B

公开(公告)日：2025-04-02

申请号：GB202407430

申请日：2022-11-23

Applicant: IBM

Inventor： RUILONG XIE ,  JULIEN FROUGIER ,  JUNLI WANG ,  DECHAO GUO ,  RUQIANG BAO ,  RISHIKESH KRISHNAN ,  BALASUBRAMANIAN PRANATHARTHIHARAN

IPC: H10D84/01 ,  H01L23/528 ,  H10D30/01 ,  H10D30/43 ,  H10D30/67 ,  H10D62/10 ,  H10D64/01 ,  H10D84/03 ,  H10D84/85 ,  H10D88/00

Abstract: A semiconductor structure is provided that includes a first FET device stacked over a second FET device, wherein the first FET device contains a first functional gate structure containing a first work function metal and the second FET device contains a second functional gate structure containing a second work function metal. In the structure, the first work function metal is absent from an area including the second work function metal, and vice versa. Thus, no shared work functional metal is present in the semiconductor structure.

公开(公告)号：GB2573711B

公开(公告)日：2021-09-29

申请号：GB201911360

申请日：2018-02-17

Applicant: IBM

Inventor： SANJAY MEHTA ,  BALASUBRAMANIAN PRANATHARTHIHARAN ,  ZHENXING BI ,  THAMARAI DEVARAJAN ,  MUTHUMANICKAM SANKARAPANDIAN

IPC: H01L21/28

Abstract: A vertical transport fin field effect transistor (VT FinFET), including one or more vertical fins on a surface of a substrate, an L-shaped or U-shaped spacer trough on the substrate adjacent to at least one of the one or more vertical fins, and a gate dielectric layer on the sidewalls of the at least one of the one or more vertical fins and the L-shaped or U-shaped spacer trough.

公开(公告)号：GB2579487A

公开(公告)日：2020-06-24

申请号：GB202001682

申请日：2018-07-16

Applicant: IBM ,  GLOBALFOUNDRIES INC ,  SAMSUNG ELECTRONICS CO LTD

Inventor： SU CHEN FAN ,  BALASUBRAMANIAN PRANATHARTHIHARAN ,  ANDREW GREENE ,  RUILONG XIE ,  MARK VICTOR RAYMOND ,  SEAN LIAN

IPC: H01L21/8238

Abstract: Techniques for forming self-aligned contacts by forming gate sidewall spacers and gates before forming the contacts are provided, in one aspect, a method of forming self-aligned contacts includes the steps of: forming multiple gate sidewall spacers on a substrate; burying the gate sidewall spacers In a dielectric; forming gate trenches by selectively rernoving the dielectric from: regions between the gate sidewall spacers in which gates will be formed; forming the gates in the gate trenches; forming contact trenches by selectively removing the dielectric from regions between the gate sidewall spacers in which the self-aligned contacts will be formed; and forming the self-aligned contacts in the contact trenches. A device structure having self-aligned contacts is also provided.