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公开(公告)号:FR2333348A1
公开(公告)日:1977-06-24
申请号:FR7632452
申请日:1976-10-18
IPC: H01L21/28 , H01L21/314 , H01L21/283 , H01L21/76 , H01L21/8247 , H01L29/41 , H01L29/43 , H01L29/51 , H01L29/78 , H01L29/788 , H01L29/792 , H01L21/31
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公开(公告)号:FR2308202A1
公开(公告)日:1976-11-12
申请号:FR7605144
申请日:1976-02-17
Applicant: IBM
Inventor: ABBAS SHAKIR A , DOCKERTY ROBERT C , POPONIAK MICHAEL R
IPC: H01L21/306 , H01L21/3063 , H01L21/308 , H01L21/322 , H01L29/06 , B41J3/04
Abstract: 1515031 Electrolytic etching of silicon INTERNATIONAL BUSINESS MACHINES CORP 3 Feb 1976 [14 April 1975] 4111/76 Heading C7B [Also in Division H1] A hole is made in a monocrystalline silicon body by providing masking with aligned apertures on parallel opposed faces of the body, providing a conductor in contact with the body through one of the openings and using this as anode in an anodic treatment to convert the entire region between the apertures to porous silicon which is then etched out to leave a hole. Typically a plurality of holes are simultaneously formed in a 100 oriented wafer which may have integrated circuitry formed on one or both faces. The masking may consist of silicon dioxide or nitride with an optical overlayer of chromium, or of silicon oxynitride or nitride-onoxide. After photoetching to form the apertures heavily doped surface regions may be formed below the apertures on one or both faces by impurity diffusion or implantation of helium ions or protons and a chromium anode layer deposited on one face. After anodic treatment in a 1:2 mixture of 49% hydrofluoric acid and distilled water the anode is removed and the porous silicon etched out.
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公开(公告)号:CA960776A
公开(公告)日:1975-01-07
申请号:CA159100
申请日:1972-12-14
Applicant: IBM
Inventor: BLEHER JOHANNES H , CHANG CHI S , DOCKERTY ROBERT C
IPC: H01L21/8247 , H01L21/00 , H01L27/10 , H01L29/74 , H01L29/788 , H01L29/792
Abstract: 1340830 Semi-conductor memory devices INTERNATIONAL BUSINESS MACHINES CORP 1 Dec 1972 [20 Dec 1971] 55489/72 Heading H1K A memory device consists of a silicon gated N-channel enhancement mode IGFET with a bi-stable switching diode consisting of a layer of niobium oxide sandwiched between layers of niobium and bismuth disposed on and wholly within the periphery of its drain region. A matrix of devices may be formed on a P-type silicon wafer by oxidizing its surface and etching the oxide to expose the device sites, depositing polycrystalline silicon overall and pattern etching it to delineate the gates and strips interconnecting them in rows and to expose the P type silicon at the source and drain sites, after which the source and drain regions are formed and the remaining polycrystalline silicon doped by donor diffusion. Electrodes are formed on these regions by alloying platinum to them, after which niobium is deposited on the drain electrode and its surface wet anodized and then coated with bismuth. The matrix is completed by provision of pairs of aluminium strips interconnecting the source and bismuth electrodes respectively in columns. Information is stored by applying word address signals to the silicon row conductors and appropriately poled bit writing signals between pairs of aluminium strips to switch the diode to its high or low resistance state. It is read out by gating the appropriate IGFET on and sensing whether or not a small voltage applied across the series circuit of the source-drain path and diode produces a current.
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公开(公告)号:CA1016663A
公开(公告)日:1977-08-30
申请号:CA214985
申请日:1974-11-29
Applicant: IBM
Inventor: ANANTHA NARASIPUR G , DOCKERTY ROBERT C
IPC: H01L29/00 , H01L29/47 , H01L29/872
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公开(公告)号:CA996279A
公开(公告)日:1976-08-31
申请号:CA182968
申请日:1973-10-09
Applicant: IBM
Inventor: BARILE CONRAD A , DOCKERTY ROBERT C , NAGARAJAN ARUNACHALA
IPC: H01L29/78 , H01L21/28 , H01L21/283 , H01L21/314 , H01L21/316 , H01L21/336 , H01L29/00 , H01L29/51
Abstract: Large threshold voltage shifts of silicon gate FET devices having a composite nitride-oxide gate dielectric are greatly reduced by subjecting the nitride to a dry oxygen annealing at temperatures between 970 DEG -1,150 DEG C prior to depositing the silicon gate electrode. Annealing at 1,050 DEG C applied for a duration of one-half to one hour produces excellent results.
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公开(公告)号:CA1079864A
公开(公告)日:1980-06-17
申请号:CA286133
申请日:1977-09-06
Applicant: IBM
Inventor: ABBAS SHAKIR A , DOCKERTY ROBERT C
IPC: H01L29/78 , H01L21/265 , H01L21/331 , H01L21/74 , H01L21/762 , H01L21/8249 , H01L27/06 , H01L29/73 , H01L21/70
Abstract: PROCESS FOR MAKING FIELD EFFECT AND BIPOLAR TRANSISTORS ON THE SAME SEMICONDUCTOR CHIP A process and the resulting structure for making metal oxide silicon field effect transistors and vertical bipolar transistors on the same semiconductor chip with the devices being dielectrically isolated from each other. The process does not require an epitaxial layer. The bipolar devices have utility as cross-chip or offchip drivers or can be utilized for analog circuitry.
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公开(公告)号:CA1061014A
公开(公告)日:1979-08-21
申请号:CA266616
申请日:1976-11-26
Applicant: IBM
Inventor: ABBAS SHAKIR A , DOCKERTY ROBERT C
IPC: H01L21/283 , H01L21/28 , H01L21/314 , H01L21/76 , H01L21/8247 , H01L29/41 , H01L29/43 , H01L29/51 , H01L29/78 , H01L29/788 , H01L29/792 , B05D5/12 , H01L29/76
Abstract: FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD FOR MAKING SAME An improved field effect transistor structure which reduces a leakage phenomenon, termed the "sidewalk" effect, between the semiconductor substrate and a conductive silicon dioxide layer disposed over the substrate. The improvement comprises forming a layer of highly resistive, silicon dioxide or silicon oxynitride, which is between the conductive oxide and the silicon nitride layer which forms a portion of the gate insulator for the field effect transistor.
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公开(公告)号:DE2458847A1
公开(公告)日:1975-07-31
申请号:DE2458847
申请日:1974-12-12
Applicant: IBM
Inventor: ANANTHA NARASIPUR G , DOCKERTY ROBERT C
IPC: H01L29/00 , H01L29/47 , H01L29/872 , H01L29/48
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