2.
    发明专利
    未知

    公开(公告)号:FR2308202A1

    公开(公告)日:1976-11-12

    申请号:FR7605144

    申请日:1976-02-17

    Applicant: IBM

    Abstract: 1515031 Electrolytic etching of silicon INTERNATIONAL BUSINESS MACHINES CORP 3 Feb 1976 [14 April 1975] 4111/76 Heading C7B [Also in Division H1] A hole is made in a monocrystalline silicon body by providing masking with aligned apertures on parallel opposed faces of the body, providing a conductor in contact with the body through one of the openings and using this as anode in an anodic treatment to convert the entire region between the apertures to porous silicon which is then etched out to leave a hole. Typically a plurality of holes are simultaneously formed in a 100 oriented wafer which may have integrated circuitry formed on one or both faces. The masking may consist of silicon dioxide or nitride with an optical overlayer of chromium, or of silicon oxynitride or nitride-onoxide. After photoetching to form the apertures heavily doped surface regions may be formed below the apertures on one or both faces by impurity diffusion or implantation of helium ions or protons and a chromium anode layer deposited on one face. After anodic treatment in a 1:2 mixture of 49% hydrofluoric acid and distilled water the anode is removed and the porous silicon etched out.

    SILICON GATE FET-NIOBIUM OXIDE DIODE-MEMORY CELL

    公开(公告)号:CA960776A

    公开(公告)日:1975-01-07

    申请号:CA159100

    申请日:1972-12-14

    Applicant: IBM

    Abstract: 1340830 Semi-conductor memory devices INTERNATIONAL BUSINESS MACHINES CORP 1 Dec 1972 [20 Dec 1971] 55489/72 Heading H1K A memory device consists of a silicon gated N-channel enhancement mode IGFET with a bi-stable switching diode consisting of a layer of niobium oxide sandwiched between layers of niobium and bismuth disposed on and wholly within the periphery of its drain region. A matrix of devices may be formed on a P-type silicon wafer by oxidizing its surface and etching the oxide to expose the device sites, depositing polycrystalline silicon overall and pattern etching it to delineate the gates and strips interconnecting them in rows and to expose the P type silicon at the source and drain sites, after which the source and drain regions are formed and the remaining polycrystalline silicon doped by donor diffusion. Electrodes are formed on these regions by alloying platinum to them, after which niobium is deposited on the drain electrode and its surface wet anodized and then coated with bismuth. The matrix is completed by provision of pairs of aluminium strips interconnecting the source and bismuth electrodes respectively in columns. Information is stored by applying word address signals to the silicon row conductors and appropriately poled bit writing signals between pairs of aluminium strips to switch the diode to its high or low resistance state. It is read out by gating the appropriate IGFET on and sensing whether or not a small voltage applied across the series circuit of the source-drain path and diode produces a current.

Patent Agency Ranking