公开(公告)号：JP2000311948A

公开(公告)日：2000-11-07

申请号：JP2000092149

申请日：2000-03-29

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： ARNDT KENNETH C ,  BRINTZINGER AXEL C ,  CONTI RICHARD A ,  COTE DONNA R ,  NARAYAN CHANDRASEKHAR ,  RAMACHANDRAN RAVIKUMAR ,  RUPP THOMAS S ,  SENTEIRU K SURIINIVUASAN

IPC: H01L21/82 ,  H01H69/02 ,  H01H85/00 ,  H01L21/8242 ,  H01L23/525 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a method and structure for generating a void fuse structure on a gate conductor stack. SOLUTION: A semiconductor substrate is provided, wherein a gate conductor stack 32 is provided on a shallow trench isolation region. Oxide layers 33 and 34 are formed on a substrate around the gate conductor stack 32, and an electric contact opening part etched to the substrate down to the oxide layer is filled with a first conductive material 40, establishing electric contact to the gate conductor stack. A conductive layer 41 of a second conductive material is allowed to stick to the oxide layer and the electric contact, and the oxide layer is anisotropically etched so that at least one etching hole, as far as the shallow trench isolation region through the oxide layer, is formed. A part 60 around the least the etching hole of the oxide layer is isotropically etched to form a void under at least a part of a conductive player pattern. The gate conductor stack comprises a fuse.

公开(公告)号：JP2001358224A

公开(公告)日：2001-12-26

申请号：JP2001133328

申请日：2001-04-27

Applicant: IBM

Inventor： KARL J REEDENSU ,  BRINTZINGER AXEL C

IPC: H01L21/768 ,  H01L21/3205 ,  H01L21/82 ,  H01L23/52 ,  H01L23/525

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming an interconnect structure with which an anti-fuse material layer is formed in the structure without using any precise lithography masking level. SOLUTION: This interconnect structure, in its inside of which an anti-fuse dielectric layer is formed, comprises a substrate 50 containing electrically conductive structures of a first level, a patterned anti-fuse dielectric layer 54 which is formed on the substrate 50 and which contains an opening to at least one of the electrically conductive structures 52 of a first level, a patterned interlevel dielectric layer 56 which is formed on the patterned anti-fuse dielectric layer 54 and which contains a plurality of vias, at least one of which is formed in the upper side of the opening with a via space, and electrically conductive structures 52 of a second level formed in the vias and the via space.