VERTICAL DRAM CELL HAVING WORD LINE SELF-ALIGNED WITH STORAGE TRENCH

    公开(公告)号:JP2001085637A

    公开(公告)日:2001-03-30

    申请号:JP2000245911

    申请日:2000-08-14

    Abstract: PROBLEM TO BE SOLVED: To obtain a vertical DRAM having a self-aligned word line conductor on the sidewall of a trench by forming a word line conductor having a sidewall aligned with the sidewall of the trench. SOLUTION: A pad nitride is removed selectively depending on the oxide 240 in an STI region 228. A screen oxide is then grown and array region p-well implantation is carried out and an N+ dopant is implanted in order to form a second diffusion region 210. Subsequently, source and drain implantation is carried out in a support region in order to form a diffusion region 288 and an oxide 242 is formed on the sidewalls 219, 233 of a word line conductor 218, 232 and on the sidewall of a support gate. Finally, a bit line conductor 244 of polysilicon is deposited for planarization. Since word line resistance is decreased, a DRAM device having improved performance can be obtained.

    PATTERNING METHOD OF SEMICONDUCTOR ELEMENT AND SEMICONDUCTOR DEVICE

    公开(公告)号:JP2000208434A

    公开(公告)日:2000-07-28

    申请号:JP2000000881

    申请日:2000-01-06

    Abstract: PROBLEM TO BE SOLVED: To form a contact of minimum feature dimensions by forming a pattern with a first parallel line and a second parallel line vertical to it inside a mask layer on a dielectric layer and forming a rectangular hole which reaches a substrate layer inside a dielectric layer according to the pattern. SOLUTION: A dielectric layer 22, a mask layer 24, a mask layer 26 and a resist layer 28 are provided sequentially on a substrate layer 20. The mask layer 26 is etched according to a line 30 of a pattern of the resist layer 28 and a parallel line 27 is formed in the mask layer 26. Then, a resist layer 32 is provided. A pattern of the resist layer 32 comprises a parallel line 34 and the line 34 is vertical to the line 27. A lattice pattern with a rectangular hole 36 is formed by anisotropically etching the mask layer 24 by using the line 27 and the line 34. The dielectric layer 22 is etched until it reaches the substrate layer 20 according to the lattice pattern.

    METHOD FOR FORMING PAIR OF MOSFETS IN DIFFERENT ELECTRICALLY INSULATING REGION OF SILICON SUBSTRATE

    公开(公告)号:JP2000068387A

    公开(公告)日:2000-03-03

    申请号:JP22160699

    申请日:1999-08-04

    Applicant: SIEMENS AG IBM

    Abstract: PROBLEM TO BE SOLVED: To provide a method for forming the pair of MOSFETs in different insulation regions of a silicon substrate. SOLUTION: The first layer of a silicon dioxide is grown on the surface of a silicon substrate, an inorganic layer is formed on a silicon dioxide layer and a photoresist layer is formed on the inorganic layer. The photoresist layer is patterned, the inorganic layer is patterned into an inorganic mask, and the photoresist layer is removed. The exposed part of the grown silicon dioxide is selectively removed by using the inorganic mask, and the inorganic mask is removed. Then the second layer of the silicon dioxide is grown on the exposed part existing below the silicon substrate, and the silicon dioxide layer is patterned into a gate oxide.

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