公开(公告)号：JP2000311948A

公开(公告)日：2000-11-07

申请号：JP2000092149

申请日：2000-03-29

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： ARNDT KENNETH C ,  BRINTZINGER AXEL C ,  CONTI RICHARD A ,  COTE DONNA R ,  NARAYAN CHANDRASEKHAR ,  RAMACHANDRAN RAVIKUMAR ,  RUPP THOMAS S ,  SENTEIRU K SURIINIVUASAN

IPC: H01L21/82 ,  H01H69/02 ,  H01H85/00 ,  H01L21/8242 ,  H01L23/525 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a method and structure for generating a void fuse structure on a gate conductor stack. SOLUTION: A semiconductor substrate is provided, wherein a gate conductor stack 32 is provided on a shallow trench isolation region. Oxide layers 33 and 34 are formed on a substrate around the gate conductor stack 32, and an electric contact opening part etched to the substrate down to the oxide layer is filled with a first conductive material 40, establishing electric contact to the gate conductor stack. A conductive layer 41 of a second conductive material is allowed to stick to the oxide layer and the electric contact, and the oxide layer is anisotropically etched so that at least one etching hole, as far as the shallow trench isolation region through the oxide layer, is formed. A part 60 around the least the etching hole of the oxide layer is isotropically etched to form a void under at least a part of a conductive player pattern. The gate conductor stack comprises a fuse.

公开(公告)号：JP2001085637A

公开(公告)日：2001-03-30

申请号：JP2000245911

申请日：2000-08-14

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： FURUKAWA TOSHIHARU ,  GRUENING ULRIKE ,  HORAK DAVID V ,  MANDELMAN JACK A ,  RADENS CARL J ,  RUPP THOMAS S

IPC: H01L27/108 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To obtain a vertical DRAM having a self-aligned word line conductor on the sidewall of a trench by forming a word line conductor having a sidewall aligned with the sidewall of the trench. SOLUTION: A pad nitride is removed selectively depending on the oxide 240 in an STI region 228. A screen oxide is then grown and array region p-well implantation is carried out and an N+ dopant is implanted in order to form a second diffusion region 210. Subsequently, source and drain implantation is carried out in a support region in order to form a diffusion region 288 and an oxide 242 is formed on the sidewalls 219, 233 of a word line conductor 218, 232 and on the sidewall of a support gate. Finally, a bit line conductor 244 of polysilicon is deposited for planarization. Since word line resistance is decreased, a DRAM device having improved performance can be obtained.

公开(公告)号：JP2000315782A

公开(公告)日：2000-11-14

申请号：JP2000123911

申请日：2000-04-25

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： RUPP THOMAS S ,  DOBUZINSKY DAVID M ,  LU ZHIJIAN

IPC: H01L21/28 ,  H01L21/768 ,  H01L21/8239 ,  H01L21/8242 ,  H01L27/00 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device which has a stable contact resistance and also has an aligned maximum allowable contact region adapted to reduced fundamental dimensions. SOLUTION: A borderless contact 11 of giga-scale fundamental dimensions is spread in a direction perpendicular to word lines 14 (in a direction parallel to bit lines 16). Formation of a borderless contact structure of another square into a rectangular structure causes reduction of a step positional deviation, thus decreasing a contact resistance and keeping its uniformity. A maximum allowable contact region can be obtained even with a positionally shifted arrangement.

公开(公告)号：JP2000208434A

公开(公告)日：2000-07-28

申请号：JP2000000881

申请日：2000-01-06

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： RUPP THOMAS S ,  ALAN THOMAS ,  FRANZ ZACHA

IPC: H01L21/302 ,  G03F7/40 ,  H01L21/027 ,  H01L21/28 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/762 ,  H01L21/768

Abstract: PROBLEM TO BE SOLVED: To form a contact of minimum feature dimensions by forming a pattern with a first parallel line and a second parallel line vertical to it inside a mask layer on a dielectric layer and forming a rectangular hole which reaches a substrate layer inside a dielectric layer according to the pattern. SOLUTION: A dielectric layer 22, a mask layer 24, a mask layer 26 and a resist layer 28 are provided sequentially on a substrate layer 20. The mask layer 26 is etched according to a line 30 of a pattern of the resist layer 28 and a parallel line 27 is formed in the mask layer 26. Then, a resist layer 32 is provided. A pattern of the resist layer 32 comprises a parallel line 34 and the line 34 is vertical to the line 27. A lattice pattern with a rectangular hole 36 is formed by anisotropically etching the mask layer 24 by using the line 27 and the line 34. The dielectric layer 22 is etched until it reaches the substrate layer 20 according to the lattice pattern.

公开(公告)号：JP2000068387A

公开(公告)日：2000-03-03

申请号：JP22160699

申请日：1999-08-04

Applicant: SIEMENS AG ,  IBM

Inventor： RUPP THOMAS S ,  KUDELKA STEPHAN ,  GAMBINO JEFFREY ,  WEYBRIGHT MARY

IPC: H01L21/308 ,  H01L21/334 ,  H01L21/8234 ,  H01L27/088

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming the pair of MOSFETs in different insulation regions of a silicon substrate. SOLUTION: The first layer of a silicon dioxide is grown on the surface of a silicon substrate, an inorganic layer is formed on a silicon dioxide layer and a photoresist layer is formed on the inorganic layer. The photoresist layer is patterned, the inorganic layer is patterned into an inorganic mask, and the photoresist layer is removed. The exposed part of the grown silicon dioxide is selectively removed by using the inorganic mask, and the inorganic mask is removed. Then the second layer of the silicon dioxide is grown on the exposed part existing below the silicon substrate, and the silicon dioxide layer is patterned into a gate oxide.