Abstract:
According to an aspect of the present inventive concept there is provided a method for manufacturing a fluid sensor device comprising: bonding a silicon-on-insulator arrangement comprising a silicon wafer, a buried oxide, a silicon layer, and a first dielectric layer, to a CMOS arrangement comprising a metallization layer and a planarized dielectric layer, wherein the bonding is performed via the first dielectric layer and the planarized dielectric layer; forming a fin-FET arrangement in the silicon layer, wherein the fin-FET arrangement is configured to function as a fluid sensitive fin-FET arrangement; removing the buried oxide and the silicon wafer; forming a contact to the metallization layer and the fin-FET arrangement, wherein the contact comprises an interconnecting structure configured to interconnect the metallization layer and the fin-FET arrangement; forming a channel comprising an inlet and an outlet, wherein the channel is configured to allow a fluid comprising an analyte to contact the fin-FET arrangement.
Abstract:
Arrays of integrated optical devices and their methods for production are provided. The devices include an integrated bandpass filter layer that comprises at least two multi-cavity filter elements with different central bandpass wavelengths. The device arrays are useful in the analysis of highly multiplexed optical reactions in large numbers at high densities, including biochemical reactions, such as nucleic acid sequencing reactions. The devices provide for the efficient and reliable coupling of optical excitation energy from an optical source to the optical reactions. Optical signals emitted from the reactions can thus be measured with high sensitivity and discrimination. The device arrays are well suited for miniaturization and high throughput.
Abstract:
In a first aspect, the present invention relates to a nanopore field-effect transistor sensor (100), comprising: i) a source region (310) and a drain region (320), defining a source-drain axis; ii) a channel region (330) between the source region (310) and the drain region (320); iii) a nanopore (400), defined as an opening in the channel region (330) which completely crosses through the channel region (330), oriented at an angle to the source-drain axis, having a first orifice (410) and a second orifice (420), and being adapted for creating a non-linear potential profile between the first (410) and second (420) orifice.
Abstract:
The invention provides an integrated semiconductor device (100) for detecting fluorescent tags, comprising a first layer (101) comprising a detector element (107), a second layer (102) located on top of the first layer (101) and comprising a rejection filter, a third layer (103) located on top of the second layer (102) and being fabricated from a dielectric material, a fourth layer (104) located on top of the third layer (103) and comprising an optical waveguide, and furthermore a fifth layer located on top of the fourth layer comprising a microfluidic channel (106). The optical waveguide is configured and positioned such that the micro-fluidic channel (106) is illuminated with an evanescent tail of excitation light guided by the optical waveguide. The rejection filter is positioned such that fluorescence from activated fluorescent tags present on top of the fourth layer (104) is filtered before falling onto the detector element (107). The rejection filter is configured to reject the wavelength range of the excitation light and configured to transmit the wavelength range of fluorescence from the activated fluorescent tags towards the detector element (107).
Abstract:
A method for fabricating a microfluidic device, comprising: a. Providing an assembly comprising: i. a first silicon substrate having a hydrophilic silicon oxide top surface comprising a microfluidic channel, ii. a second silicon substrate, having a hydrophilic silicon oxide bottom surface directly bonded on the top surface of the first silicon substrate, and comprising fluidic access holes giving fluidic access to the microfluidic channel, and
b. Exposing the assembly to oxidative species comprising one or more oxygen atoms and to heat so as to form silicon oxide at a surface of the access holes and of the microfluidic channel.
Abstract:
The present disclosure relates to semiconductor devices for detecting fluorescent particles. At least one embodiment relates to an integrated semiconductor device for detecting fluorescent tags. The device includes a first layer, a second layer, a third layer, a fourth layer, and a fifth layer. The first layer includes a detector element. The second layer includes a rejection filter. The third layer is fabricated from dielectric material. The fourth layer is an optical waveguide configured and positioned such that a top surface of the fourth layer is illuminated with an evanescent tail of excitation light guided by the optical waveguide when the fluorescent tags are present. The fifth layer includes a microfluidic channel. The optical waveguide is configured and positioned such that the microfluidic channel is illuminated with the evanescent tail. The detector element is positioned such that light from activated fluorescent tags can be received.
Abstract:
In a first aspect, the present invention relates to a nanopore field-effect transistor sensor (100), comprising i. a source region (310) and a drain region (320), defining a source-drain axis; ii. a channel region (330) between the source region (310) and the drain region (320); iii. a nanopore (400) through the channel region (330), oriented at an angle to the source-drain axis, having a first orifice (410) and a second orifice (420), and being adapted for creating a non-linear potential profile between the first (410) and second (420) orifice.
Abstract:
According to an aspect of the present inventive concept there is provided a method for manufacturing a fluid sensor device comprising: bonding a silicon-on-insulator arrangement comprising a silicon wafer, a buried oxide, a silicon layer, and a first dielectric layer, to a CMOS arrangement comprising a metallization layer and a planarized dielectric layer, wherein the bonding is performed via the first dielectric layer and the planarized dielectric layer; forming a fin-FET arrangement in the silicon layer, wherein the fin-FET arrangement is configured to function as a fluid sensitive fin-FET arrangement; removing the buried oxide and the silicon wafer; forming a contact to the metallization layer and the fin-FET arrangement, wherein the contact comprises an interconnecting structure configured to interconnect the metallization layer and the fin-FET arrangement; forming a channel comprising an inlet and an outlet, wherein the channel is configured to allow a fluid comprising an analyte to contact the fin-FET arrangement.
Abstract:
Micro-mirror arrays configured for use in a variable focal length lens are described herein. An example variable focal length lens comprises a micro-mirror array having a plurality of micro-mirror elements arranged in at least a first section and a second section. Each micro-mirror element has a tilt axis and comprises, on each of two opposing sides of the tilt axis, (i) at least one actuation electrode, (ii) at least one measurement electrode, and (iii) at least one stopper. Additionally, each micro-mirror element in the first section has a first tilt angle range, and each micro-mirror element in the second section has a second tilt angle range, with the first tilt angle range being less than the second tilt angle range.
Abstract:
Method for forming a nanopore transistor, comprising: a. Forming an aperture in a filler material by: i. providing a fin comprising a semiconductor layer and a top layer; ii. pattering the top layer to form a pillar; iii. embedding the pillar in a filler material; iv. removing the pillar, leaving an aperture; v. lining the aperture with a spacer material;
b. forming a nanopore by etching through the aperture, c. Lining the nanopore with a dielectric, d. Forming a source and a drain by either: i. Between steps a.ii. and a.iii., doping the bottom semiconductor layer by using the pillar as a mask, or ii. After step c., - filling the aperture with a sealing material, thereby forming a post; - removing the filler material; - doping the bottom semiconductor layer by using the post as a mask; and - removing the sealing material.