公开(公告)号：DE102005045636A1

公开(公告)日：2007-03-29

申请号：DE102005045636

申请日：2005-09-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： POLEI VERONIKA ,  BACH LARS ,  OLLIGS DOMINIK ,  MUELLER TORSTEN

IPC: H01L27/115 ,  G11C16/02 ,  H01L21/8247

Abstract: A semiconductor substrate is provided with a recess. A memory layer or memory layer sequence is applied to sidewalls and the bottom of the recess. The memory layer is formed into two separate portions at opposite sidewalls of the recess either by reducing the memory layer to sidewall spacers or by forming sidewall spacers and removing portions of the memory layer that are not covered by the spacers. A gate electrode is applied into the recess, and source/drain regions are formed by an implantation of doping atoms adjacent to the sidewalls of the recess and the remaining portions of the memory layer. The memory layer can especially be a dielectric material suitable for charge-trapping.

公开(公告)号：DE102006017795A1

公开(公告)日：2007-10-11

申请号：DE102006017795

申请日：2006-04-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BACH LARS

IPC: H01L27/115 ,  H01L21/8247

公开(公告)号：DE102005060083A1

公开(公告)日：2007-06-28

申请号：DE102005060083

申请日：2005-12-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BACH LARS

IPC: H01L27/115 ,  H01L21/8247

Abstract: Component has one of insulating layers (10) arranged at an upper surface (5) of a rib. The insulating layer is activated at the upper surface of the rib and a charge capturing layer (11). A word line (2) covers the insulating layer and the charge capturing layer. A conducting layer comprises doped poly silicon. An insulating filling comprises silicon oxide, and a cap layer is provided with silicon nitride. Lines comprise phosphorous, and a substrate is provided with a line shaped region. A trench insulator filling comprises boron phosphorous silicate glass. Independent claims are also included for: (a) designing a semiconductor memory unit (b) memory cell comprising a rib (c) designing a memory cell.

公开(公告)号：DE102005053509A1

公开(公告)日：2007-04-05

申请号：DE102005053509

申请日：2005-11-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： OLLIGS DOMINIK ,  MIKOLAJICK THOMAS ,  DEPPE JOACHIM ,  MUELLER TORSTEN ,  NAGEL NICOLAS ,  BACH LARS ,  POLEI VERONIKA ,  BOUBEKEUR HOCINE

IPC: H01L21/8239 ,  G11C5/06 ,  H01L21/768 ,  H01L21/8247

Abstract: In a process to manufacture a semiconductor product, word guides are positioned above the substrate in a first direction (X) at intervals parallel to the substrate surface (22). Contact structures and first filling structures are formed between the word guides. The contact structures are of a defined width along the first direction (X) and are separated by the first filling structure. A mask is formed with apertures in a second direction (y) parallel to the substrate surface (22). The contact structures are wet-etched through the apertures (12) and the resulting detents are filled with a second agent (5), followed by formation of the bit guides that make contact with the structure (3) along the second direction.

公开(公告)号：DE102005037029A1

公开(公告)日：2007-01-11

申请号：DE102005037029

申请日：2005-08-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： OLLIGS DOMINIK ,  MIKOLAJICK THOMAS ,  NAGEL NICOLAS ,  BACH LARS ,  POLEI VERONIKA ,  MUELLER TORSTEN

IPC: H01L21/8247 ,  G11C16/02

Abstract: A semiconductor product includes, a substrate with a first dielectric layer having contact hole fillings for contacting active areas in the substrate. A second dielectric layer with contact holes is provided therein. The contact holes have a width in a first lateral direction. The product further includes conductive lines, each conductive line passing over contact holes in the second dielectric layer and contacting a plurality of contact hole fillings in the first dielectric layer. The conductive lines have a width, in the first lateral direction, that is smaller than the width of the contact holes of the second dielectric layer. The conductive lines are in direct mechanical contact with the contact hole fillings and thereby remove the need to provide any conventional "contact to interconnect" structures.