公开(公告)号：WO2004068578A3

公开(公告)日：2004-10-28

申请号：PCT/DE2004000042

申请日：2004-01-15

Applicant: INFINEON TECHNOLOGIES AG ,  GRATZ ACHIM ,  POLEI VERONIKA ,  ROEHRICH MAYK

Inventor： GRATZ ACHIM ,  POLEI VERONIKA

IPC: H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: The invention relates to a method for producing bit lines for UCP flash memories comprising a floating gate arrangement arranged on a substrate and an insulation arranged in the substrate under the floating gate arrangement. Initially, the floating gate is produced, after photolithography, by etching a separated polysilicon layer deposited on the total surface of the substrate. The aim of the invention is to provide a method wherein cell size can be reduced without significantly increasing production costs and wherein the bit lines survive the temperature budget of the sequence process without being damaged. As a result, the bit line (13), embodied as a buried bit line made of a temperature resistant material, is arranged in a silicon substrate (2) or in the insulation (3) of the active area below the floating gate (1) by automatic adjustment therewith (2). The already structured floating gate (1) is used as an etching mask for producing, by etching in insulation (3), a trench (6) which is subsequently filled with a low impedance material.

Abstract translation: 本发明涉及一种用于为UCP快闪存储器位线的制造具有设置在基板上浮动栅极组件和所述浮置栅极器件下的衬底中的隔离方法，其特征在于，最初的浮置栅极通过现有的光刻通过在基板上蚀刻 产生位于整个区域上方的沉积多晶硅层。 本发明的目的是提供一种方法，通过该方法可以实现单元尺寸的减小，生产成本受到的影响可以忽略不计，并且位线在后续工艺的温度预算下不会受到损坏。 实现，即，位线（13）在硅衬底（2）由耐温度变化的材料掩埋位线或绝缘（3）内的浮置栅（1）是，自对准于该布置下的有源区。 在这种情况下，使用已经构造的浮置栅极（1）作为蚀刻掩模将沟槽（6）蚀刻到绝缘体（3）中，然后用低电阻材料填充该蚀刻掩模。

公开(公告)号：DE10232938A1

公开(公告)日：2004-02-12

申请号：DE10232938

申请日：2002-07-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GRATZ ACHIM ,  POLEI VERONIKA ,  ROEHRICH MAYK

IPC: H01L21/225 ,  H01L21/74 ,  H01L21/8247 ,  H01L21/768

公开(公告)号：DE10111989C2

公开(公告)日：2003-11-06

申请号：DE10111989

申请日：2001-03-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KRIZ JAKOB ,  GRATZ ACHIM ,  POLEI VERONIKA ,  SPERL IRENE ,  RUDER THOMAS

IPC: H01L21/02 ,  H01L21/28 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/485 ,  H01L23/60

公开(公告)号：DE102006010981A1

公开(公告)日：2007-09-06

申请号：DE102006010981

申请日：2006-03-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： POLEI VERONIKA ,  OLLIGS DOMINIK

IPC: H01L21/311 ,  H01L21/308 ,  H01L21/336

Abstract: A layer sequence with lateral boundaries, especially a gate electrode stack, comprises a cover layer between a metal layer and a top layer that is provided as a hardmask. The cover layer, which is preferably polysilicon, enables the application of a cleaning agent to remove a resist layer, clean the hardmask and remove deposits of the material of the top layer produced in the structuring of the hardmask, before the layer sequence is structured using the hardmask. The cover layer protects the metal layer, which could otherwise be damaged by the cleaning agent.

公开(公告)号：DE102006008503A1

公开(公告)日：2007-06-28

申请号：DE102006008503

申请日：2006-02-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MUELLER TORSTEN ,  OLLIGS DOMINIK ,  KUESTERS KARL-HEINZ ,  MIKOLAJICK THOMAS ,  POLEI VERONIKA ,  WILLER JOSEF

IPC: H01L21/8247 ,  G11C16/00

Abstract: A method for fabricating stacked non-volatile memory cells and non-volatile memory cell arrays are disclosed. A semiconductor wafer is provided having a charge-trapping layer and a conductive layer deposited on the surface of the semiconductor wafer. Using a mask layer on top of the conductive layer, contact holes are formed into which a contact fill material is deposited. A further conductive layer is deposited on the surface of the semiconductor wafer and is patterned so as to form word lines. The contact fill material is connected to a contact plug using the contact holes with the contact fill material as a landing pad.

公开(公告)号：DE102005045636A1

公开(公告)日：2007-03-29

申请号：DE102005045636

申请日：2005-09-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： POLEI VERONIKA ,  BACH LARS ,  OLLIGS DOMINIK ,  MUELLER TORSTEN

IPC: H01L27/115 ,  G11C16/02 ,  H01L21/8247

Abstract: A semiconductor substrate is provided with a recess. A memory layer or memory layer sequence is applied to sidewalls and the bottom of the recess. The memory layer is formed into two separate portions at opposite sidewalls of the recess either by reducing the memory layer to sidewall spacers or by forming sidewall spacers and removing portions of the memory layer that are not covered by the spacers. A gate electrode is applied into the recess, and source/drain regions are formed by an implantation of doping atoms adjacent to the sidewalls of the recess and the remaining portions of the memory layer. The memory layer can especially be a dielectric material suitable for charge-trapping.

公开(公告)号：DE102004062288B3

公开(公告)日：2006-07-13

申请号：DE102004062288

申请日：2004-12-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： STEIN VON KAMIENSKI ELARD ,  RIEDEL STEPHAN ,  HABERKERN ROLAND ,  POLEI VERONIKA ,  KNOEFLER ROMAN ,  TEMPEL GEORG

IPC: H01L21/8247

Abstract: The method aims at improving the charge confinement of the memory layer at the edges facing the regions of buried bitlines. After the deposition of the memory layer between confinement layers and the implantation of dopants for bitlines and source/drain regions, an oxidation of semiconductor material to form upper bitline isolation regions takes place. By this method, additional oxide regions are produced at the edges of the memory layer in the same oxidation step. Either a silicon layer may be deposited and reduced to sidewall spacers, which are subsequently oxidized; or recesses are etched into the memory layer and subsequently filled with semiconductor oxide.

公开(公告)号：DE10043215C1

公开(公告)日：2002-04-18

申请号：DE10043215

申请日：2000-09-01

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LEHR MATTHIAS UWE ,  POLEI VERONIKA ,  SPERL IRENE ,  SCHILLING UWE

IPC: H01L23/52 ,  H01L21/3205 ,  H01L21/82 ,  H01L23/525 ,  H01L21/768

Abstract: A method for producing antifuse structures and antifuses by which adjacent conductive regions can be selectively electrically connected involve the application of a sacrificial layer to a first conductive region. The sacrificial layer is patterned with the aid of a photolithographic method. A fuse layer is applied and the sacrificial layer is then removed. A non-conductive layer is applied and a conductive material is introduced in an opening in the non-conductive layer for the purpose of forming a second conductive region.

公开(公告)号：DE10205079A1

公开(公告)日：2003-08-28

申请号：DE10205079

申请日：2002-02-07

Applicant: INFINEON TECHNOLOGIES AG ,  INGENTIX GMBH & CO KG

Inventor： POLEI VERONIKA ,  WILLER JOSEF

IPC: H01L21/28 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/792 ,  H01L21/8247

Abstract: The memory cell has a source region and a drain region in semiconductor material and, above a channel region between the source and drain regions, a three-layered layer structure with a storage layer between boundary layers and a gate electrode arranged thereon. The storage layer is replaced above the channel region by an etching layer made of Al2O3. During fabrication, the etching layer is etched out laterally and the second boundary layer is thus undercut. The resulting interspaces are filled with the material of the storage layer. The provision of suitable spacers makes it possible to define the dimensions of the memory cell.

公开(公告)号：DE10205079B4

公开(公告)日：2008-01-03

申请号：DE10205079

申请日：2002-02-07

Applicant: INFINEON TECHNOLOGIES AG ,  INFINEON TECHNOLOGIES FLASH GM

Inventor： POLEI VERONIKA ,  WILLER JOSEF

IPC: H01L21/8247 ,  H01L21/28 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/792

Abstract: The memory cell has a source region and a drain region in semiconductor material and, above a channel region between the source and drain regions, a three-layered layer structure with a storage layer between boundary layers and a gate electrode arranged thereon. The storage layer is replaced above the channel region by an etching layer made of Al2O3. During fabrication, the etching layer is etched out laterally and the second boundary layer is thus undercut. The resulting interspaces are filled with the material of the storage layer. The provision of suitable spacers makes it possible to define the dimensions of the memory cell.