公开(公告)号：DE102006008503A1

公开(公告)日：2007-06-28

申请号：DE102006008503

申请日：2006-02-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MUELLER TORSTEN ,  OLLIGS DOMINIK ,  KUESTERS KARL-HEINZ ,  MIKOLAJICK THOMAS ,  POLEI VERONIKA ,  WILLER JOSEF

IPC: H01L21/8247 ,  G11C16/00

Abstract: A method for fabricating stacked non-volatile memory cells and non-volatile memory cell arrays are disclosed. A semiconductor wafer is provided having a charge-trapping layer and a conductive layer deposited on the surface of the semiconductor wafer. Using a mask layer on top of the conductive layer, contact holes are formed into which a contact fill material is deposited. A further conductive layer is deposited on the surface of the semiconductor wafer and is patterned so as to form word lines. The contact fill material is connected to a contact plug using the contact holes with the contact fill material as a landing pad.

公开(公告)号：DE102005042331B3

公开(公告)日：2007-04-05

申请号：DE102005042331

申请日：2005-09-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PRITCHARD DAVID ,  KLEINT CHRISTOPH ANDREAS ,  OLLIGS DOMINIK ,  BOUBEKEUR HOCINE ,  MUELLER TORSTEN

IPC: H01L21/8247

Abstract: Dielectric gratings are formed between the word line stacks. Spacers are applied to the sidewalls of the word line stacks and the dielectric gratings. In the openings between the spacers, silicon is epitaxially grown on the upper surfaces of source/drain regions, which are implanted self-aligned to the word line stacks. A silicide is formed on the grown silicon, and a metal layer is applied and structured to form local interconnects, which connect the source/drain regions to upper bit lines.

公开(公告)号：DE102005045636A1

公开(公告)日：2007-03-29

申请号：DE102005045636

申请日：2005-09-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： POLEI VERONIKA ,  BACH LARS ,  OLLIGS DOMINIK ,  MUELLER TORSTEN

IPC: H01L27/115 ,  G11C16/02 ,  H01L21/8247

Abstract: A semiconductor substrate is provided with a recess. A memory layer or memory layer sequence is applied to sidewalls and the bottom of the recess. The memory layer is formed into two separate portions at opposite sidewalls of the recess either by reducing the memory layer to sidewall spacers or by forming sidewall spacers and removing portions of the memory layer that are not covered by the spacers. A gate electrode is applied into the recess, and source/drain regions are formed by an implantation of doping atoms adjacent to the sidewalls of the recess and the remaining portions of the memory layer. The memory layer can especially be a dielectric material suitable for charge-trapping.

公开(公告)号：DE102006006570A1

公开(公告)日：2007-08-09

申请号：DE102006006570

申请日：2006-02-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WILLER JOSEF ,  IACONO STEPHANIE ,  MUELLER TORSTEN

IPC: H01L21/768

Abstract: A periodic pattern of conductor tracks with broader interspaces is produced by the application of a totally periodic pattern and subsequent removal of individual conductor tracks. An alternative method comprises the formation of a completely periodic hardmask, from which individual parts are removed. The modified hardmask is then used to etch a periodic pattern of conductor tracks with intermediate broader spaces.

公开(公告)号：DE102005048197B3

公开(公告)日：2007-04-26

申请号：DE102005048197

申请日：2005-10-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： OLLIGS DOMINIK ,  MUELLER TORSTEN ,  PARASCANDOLA STEFANO ,  RIEDEL STEPHAN ,  CASPARY DIRK ,  KNOEFLER ROMAN

IPC: H01L27/115 ,  H01L21/8247

Abstract: The bit lines are produced by an implantation of a dopant by means of a sacrificial hard mask layer, which is later replaced with the gate electrodes formed of polysilicon in the memory cell array. Striplike areas of the memory cell array, which run transversely to the bit lines, are reserved by a blocking layer to be occupied by the bit line contacts. In these areas, the hard mask is used to form contact holes, which are self-aligned with the implanted buried bit lines. Between the blocked areas, the word lines are arranged normally to the bit lines.

公开(公告)号：DE102006003393A1

公开(公告)日：2007-04-12

申请号：DE102006003393

申请日：2006-01-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： OLLIGS DOMINIK ,  KUESTERS KARL-HEINZ ,  MUELLER TORSTEN ,  MIKOLAJICK THOMAS ,  WILLER JOSEF

IPC: H01L21/8247

Abstract: A method is provided for fabricating stacked non-volatile memory cells. A semiconductor wafer is provided having a plurality of diffusion regions forming buried bit lines. A charge-trapping layer and a conductive layer are deposited on the surface of the semiconductor wafer. Using a mask layer on top of the conductive layer, contact holes are formed wherein an insulating layer is formed. An etch stop layer is deposited on the surface of the semiconductor wafer. Above the etch stop layer, a dielectric layer is deposited and is patterned so as to form contact holes. Subsequently, the contact holes are enlarged through the etch stop layer and the insulating layer to the buried bit lines.

公开(公告)号：DE102006018235B3

公开(公告)日：2007-10-11

申请号：DE102006018235

申请日：2006-04-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： REGUL JOERN ,  MUELLER TORSTEN ,  KAPTEYN CHRISTIAN ,  BAARS PETER ,  MUEMMLER KLAUS

IPC: H01L27/115 ,  G11C5/06 ,  H01L21/8247

Abstract: The component has a substrate at a main side, where lower bit lines (LBL1- LBL6) are formed in the substrate and are arranged parallel to each other at a distance. Word lines (WL1- WL10) are arranged over the lower bit lines parallel to each other at a distance and transverse to the lower bit lines. A gate-dielectric arranged between the word lines and cell bodies includes a memory layer as a memory medium. Lower source and/or drain regions are formed at lower lines of the bodies adjacent to the lower bit lines, and upper source and/or drain regions are formed in upper lines of the bodies. An independent claim is also included for a method for manufacturing semiconductor memory components.

公开(公告)号：DE102005053509A1

公开(公告)日：2007-04-05

申请号：DE102005053509

申请日：2005-11-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： OLLIGS DOMINIK ,  MIKOLAJICK THOMAS ,  DEPPE JOACHIM ,  MUELLER TORSTEN ,  NAGEL NICOLAS ,  BACH LARS ,  POLEI VERONIKA ,  BOUBEKEUR HOCINE

IPC: H01L21/8239 ,  G11C5/06 ,  H01L21/768 ,  H01L21/8247

Abstract: In a process to manufacture a semiconductor product, word guides are positioned above the substrate in a first direction (X) at intervals parallel to the substrate surface (22). Contact structures and first filling structures are formed between the word guides. The contact structures are of a defined width along the first direction (X) and are separated by the first filling structure. A mask is formed with apertures in a second direction (y) parallel to the substrate surface (22). The contact structures are wet-etched through the apertures (12) and the resulting detents are filled with a second agent (5), followed by formation of the bit guides that make contact with the structure (3) along the second direction.

公开(公告)号：DE102005037029A1

公开(公告)日：2007-01-11

申请号：DE102005037029

申请日：2005-08-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： OLLIGS DOMINIK ,  MIKOLAJICK THOMAS ,  NAGEL NICOLAS ,  BACH LARS ,  POLEI VERONIKA ,  MUELLER TORSTEN

IPC: H01L21/8247 ,  G11C16/02

Abstract: A semiconductor product includes, a substrate with a first dielectric layer having contact hole fillings for contacting active areas in the substrate. A second dielectric layer with contact holes is provided therein. The contact holes have a width in a first lateral direction. The product further includes conductive lines, each conductive line passing over contact holes in the second dielectric layer and contacting a plurality of contact hole fillings in the first dielectric layer. The conductive lines have a width, in the first lateral direction, that is smaller than the width of the contact holes of the second dielectric layer. The conductive lines are in direct mechanical contact with the contact hole fillings and thereby remove the need to provide any conventional "contact to interconnect" structures.