公开(公告)号：DE102006023682A1

公开(公告)日：2007-10-18

申请号：DE102006023682

申请日：2006-05-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： OLLIGS DOMINIK ,  MIKALO RICARDO PABLO ,  BEUG FLORIAN

IPC: H01L21/8247 ,  H01L27/115

Abstract: A field-effect transistor is formed that has spacers formed by etching openings into a conductive layer and filling the openings with spacer material. The openings are formed together with a gate web in the conductive layer, wherein the gate web is surrounded by the openings on at least two sides. The spacers serve to define lightly doped drain regions arranged in the underlying substrate between a highly doped drain region and a channel region of the transistor. The transistor thus formed is specifically suited for providing high-voltage currents to memory cells of a non-volatile memory array.

公开(公告)号：DE102005048197B3

公开(公告)日：2007-04-26

申请号：DE102005048197

申请日：2005-10-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： OLLIGS DOMINIK ,  MUELLER TORSTEN ,  PARASCANDOLA STEFANO ,  RIEDEL STEPHAN ,  CASPARY DIRK ,  KNOEFLER ROMAN

IPC: H01L27/115 ,  H01L21/8247

Abstract: The bit lines are produced by an implantation of a dopant by means of a sacrificial hard mask layer, which is later replaced with the gate electrodes formed of polysilicon in the memory cell array. Striplike areas of the memory cell array, which run transversely to the bit lines, are reserved by a blocking layer to be occupied by the bit line contacts. In these areas, the hard mask is used to form contact holes, which are self-aligned with the implanted buried bit lines. Between the blocked areas, the word lines are arranged normally to the bit lines.

公开(公告)号：DE102006003393A1

公开(公告)日：2007-04-12

申请号：DE102006003393

申请日：2006-01-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： OLLIGS DOMINIK ,  KUESTERS KARL-HEINZ ,  MUELLER TORSTEN ,  MIKOLAJICK THOMAS ,  WILLER JOSEF

IPC: H01L21/8247

Abstract: A method is provided for fabricating stacked non-volatile memory cells. A semiconductor wafer is provided having a plurality of diffusion regions forming buried bit lines. A charge-trapping layer and a conductive layer are deposited on the surface of the semiconductor wafer. Using a mask layer on top of the conductive layer, contact holes are formed wherein an insulating layer is formed. An etch stop layer is deposited on the surface of the semiconductor wafer. Above the etch stop layer, a dielectric layer is deposited and is patterned so as to form contact holes. Subsequently, the contact holes are enlarged through the etch stop layer and the insulating layer to the buried bit lines.

公开(公告)号：DE102006019122B4

公开(公告)日：2008-03-06

申请号：DE102006019122

申请日：2006-04-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： OLLIGS DOMINIK

IPC: H01L21/8247 ,  H01L27/115

Abstract: The invention in one of the embodiments refers to a method for forming an integrated memory device, the method including a forming a plurality of bitlines, wherein forming the plurality of bitlines includes forming diffusion lines in a substrate, forming an electrically conductive silicidation barrier layer on a substrate surface exposed, and depositing a conductive layer comprising a metal on the silicidation barrier layer.

公开(公告)号：DE102006010981A1

公开(公告)日：2007-09-06

申请号：DE102006010981

申请日：2006-03-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： POLEI VERONIKA ,  OLLIGS DOMINIK

IPC: H01L21/311 ,  H01L21/308 ,  H01L21/336

Abstract: A layer sequence with lateral boundaries, especially a gate electrode stack, comprises a cover layer between a metal layer and a top layer that is provided as a hardmask. The cover layer, which is preferably polysilicon, enables the application of a cleaning agent to remove a resist layer, clean the hardmask and remove deposits of the material of the top layer produced in the structuring of the hardmask, before the layer sequence is structured using the hardmask. The cover layer protects the metal layer, which could otherwise be damaged by the cleaning agent.

公开(公告)号：DE102006008503A1

公开(公告)日：2007-06-28

申请号：DE102006008503

申请日：2006-02-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MUELLER TORSTEN ,  OLLIGS DOMINIK ,  KUESTERS KARL-HEINZ ,  MIKOLAJICK THOMAS ,  POLEI VERONIKA ,  WILLER JOSEF

IPC: H01L21/8247 ,  G11C16/00

Abstract: A method for fabricating stacked non-volatile memory cells and non-volatile memory cell arrays are disclosed. A semiconductor wafer is provided having a charge-trapping layer and a conductive layer deposited on the surface of the semiconductor wafer. Using a mask layer on top of the conductive layer, contact holes are formed into which a contact fill material is deposited. A further conductive layer is deposited on the surface of the semiconductor wafer and is patterned so as to form word lines. The contact fill material is connected to a contact plug using the contact holes with the contact fill material as a landing pad.

公开(公告)号：DE102005042331B3

公开(公告)日：2007-04-05

申请号：DE102005042331

申请日：2005-09-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PRITCHARD DAVID ,  KLEINT CHRISTOPH ANDREAS ,  OLLIGS DOMINIK ,  BOUBEKEUR HOCINE ,  MUELLER TORSTEN

IPC: H01L21/8247

Abstract: Dielectric gratings are formed between the word line stacks. Spacers are applied to the sidewalls of the word line stacks and the dielectric gratings. In the openings between the spacers, silicon is epitaxially grown on the upper surfaces of source/drain regions, which are implanted self-aligned to the word line stacks. A silicide is formed on the grown silicon, and a metal layer is applied and structured to form local interconnects, which connect the source/drain regions to upper bit lines.

公开(公告)号：DE102005045636A1

公开(公告)日：2007-03-29

申请号：DE102005045636

申请日：2005-09-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： POLEI VERONIKA ,  BACH LARS ,  OLLIGS DOMINIK ,  MUELLER TORSTEN

IPC: H01L27/115 ,  G11C16/02 ,  H01L21/8247

Abstract: A semiconductor substrate is provided with a recess. A memory layer or memory layer sequence is applied to sidewalls and the bottom of the recess. The memory layer is formed into two separate portions at opposite sidewalls of the recess either by reducing the memory layer to sidewall spacers or by forming sidewall spacers and removing portions of the memory layer that are not covered by the spacers. A gate electrode is applied into the recess, and source/drain regions are formed by an implantation of doping atoms adjacent to the sidewalls of the recess and the remaining portions of the memory layer. The memory layer can especially be a dielectric material suitable for charge-trapping.

公开(公告)号：DE102005036548A1

公开(公告)日：2007-01-18

申请号：DE102005036548

申请日：2005-08-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： NAGEL NICOLAS ,  OLLIGS DOMINIK

IPC: H01L21/8247

公开(公告)号：DE102006019122A1

公开(公告)日：2007-10-11

申请号：DE102006019122

申请日：2006-04-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： OLLIGS DOMINIK

IPC: H01L21/8247 ,  H01L27/115

Abstract: The invention in one of the embodiments refers to a method for forming an integrated memory device, the method including a forming a plurality of bitlines, wherein forming the plurality of bitlines includes forming diffusion lines in a substrate, forming an electrically conductive silicidation barrier layer on a substrate surface exposed, and depositing a conductive layer comprising a metal on the silicidation barrier layer.