公开(公告)号：JP2001077203A

公开(公告)日：2001-03-23

申请号：JP2000237577

申请日：2000-08-04

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BAENISCH ANDREAS ,  KLING SABINE

IPC: H01L21/768 ,  H01L21/3213 ,  H01L21/82 ,  H01L23/522 ,  H01L23/528

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor chip, comprising at least two metal lines, of two different metalized surfaces, extending orthogonally each other, reducing the required space for minimize the election movement effect for mutual contact connection. SOLUTION: In this semiconductor chip, at least one metal line 1 of a first metalized surface and a metal line 2 of a second metalized surface are provided. The metalized surfaces are parallel to each other, while at least one conductive contact point 3 is provided between the metal lines. The metal lines are orthogonal to each other in a first region, where they are not contact-connected via the contact point, while being parallel to each other and being diagonal with respect to the direction of metal line in the first region, in a second region 20, where they are contact-connected via the contact point.

公开(公告)号：DE10051719A1

公开(公告)日：2002-05-08

申请号：DE10051719

申请日：2000-10-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KLING SABINE ,  SAVIGNAC DOMINIQUE ,  MOLL HANS-PETER ,  HAFFNER HENNING ,  HIETSCHOLD ELKE

IPC: H01L21/768 ,  H01L21/8242 ,  H01L23/528 ,  H01L27/02 ,  H01L27/105 ,  H01L21/312 ,  H01L21/105 ,  H01L21/82 ,  G11C5/06 ,  H01L27/10

Abstract: The method involves using a lithographic process, whereby photo-lacquer structures are formed on the semiconducting substrate (5) to define dummy circuit structures. If an envisaged dummy structure (4) is smaller than a minimum size determined by the smallest required adhesive surface for photo-lacquer the first dummy structure is combined with a second to exceed the minimum size. An independent claim is also included for the following: a semiconducting substrate with functional circuit structures and dummy structures.

公开(公告)号：DE10124753B4

公开(公告)日：2006-06-08

申请号：DE10124753

申请日：2001-05-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PFEFFERL PETER ,  SAVIGNAC DOMINIQUE ,  SCHNEIDER HELMUT ,  CHRYSOSTOMIDES ATHANASIA ,  KLING SABINE

IPC: G11C7/06

Abstract: The invention provides a method in which a binary memory cell signal from a; least one memory cell is applied to at least one bit line pair (201t, 201b), the binary memory cell signal from the memory tell is switched through via the bit line pair (201t, 201b) to at least one sense amplifier (202), a binary output signal of the sense amplifier (202) is switched through to a local data line pair (205) as a binary intermediate signal, the binary intermediate signal on the local data line pair (205) is switched through to at least one main data line pair (208) by means of a main data line switching transistor pair (209) in a manner dependent on a row control signal fed via a row control line (210), the main data line switching transistor pair (209) being arranged in the through-plating regions formed between the memory cell arrays.

公开(公告)号：DE10126567B4

公开(公告)日：2006-01-05

申请号：DE10126567

申请日：2001-05-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KLING SABINE ,  BAENISCH ANDREAS

IPC: G11C8/08 ,  G11C17/18 ,  H01L23/525 ,  H01L23/58 ,  H01L27/10

公开(公告)号：DE10228128B4

公开(公告)日：2004-09-23

申请号：DE10228128

申请日：2002-06-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BAENISCH ANDREAS ,  OBERMAIER WERNER ,  KLING SABINE

IPC: G06F3/06 ,  G06F5/00 ,  G06F7/00 ,  G11C8/00

Abstract: The invention relates to two methods for reading and two methods for storing data, and also to an apparatus for compressing data and decompressing data which are provided for storage by a computer system 51 on a bulk memory 60 of the random access type, which computer system provides the data for storage on a bulk memory on the basis of the rules of a file system, where the data are organized in data blocks, where the data blocks contain organization information for managing the data blocks and contain the user information which is to be stored, where cohesive user information areas can be distributed over a plurality of data blocks which are then concatenated to one another using their organization information.

公开(公告)号：DE10124753A1

公开(公告)日：2002-12-12

申请号：DE10124753

申请日：2001-05-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PFEFFERL PETER ,  SAVIGNAC DOMINIQUE ,  SCHNEIDER HELMUT ,  CHRYSOSTOMIDES ATHANASIA ,  KLING SABINE

IPC: G11C7/06

Abstract: The method involves applying a binary memory cell signal(s) to a bit line pair(s), connecting the signal to a detection amplifier(s) depending on a cell field control signal(s), connecting a binary output signal to a local data line pair as a binary intermediate signal depending on a column control signal, connecting the intermediate signal to a main data line pair(s) depending on a line control signal and outputting a binary output signal. The method involves applying at least one binary memory cell signal to at least one bit line pair (201t,201b), connecting the signal to at least one detection amplifier (202-0 to 202-7) depending on at least one cell field control signal, connecting a binary output signal to a local data line pair as a binary intermediate signal depending on a column control signal, connecting the intermediate signal to at least one main data line pair depending on a line control signal and outputting a binary output signal

公开(公告)号：DE10126567A1

公开(公告)日：2002-12-05

申请号：DE10126567

申请日：2001-05-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KLING SABINE ,  BAENISCH ANDREAS

IPC: G11C8/08 ,  G11C17/18 ,  H01L23/58 ,  H01L23/525 ,  H01L27/10

Abstract: The integrated circuit comprises one or more capacitors (P) and a switch (SW,L,FU) for (DE) coupling the capacitor to and from the circuit. A detector (DE) picks-up at lest one preset state of the circuit which requires the (DE) coupling of the capacitor, and transmits a detector signal (SIG). Typically the integrated circuit is of driver type and the preset state is short-circuiting of the capacitor. The switch may contain a FET and a safety fuse and/or an anti-safety fuse.

公开(公告)号：DE10228128A1

公开(公告)日：2004-01-22

申请号：DE10228128

申请日：2002-06-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BAENISCH ANDREAS ,  OBERMAIER WERNER ,  KLING SABINE

IPC: G06F3/06 ,  G06F5/00 ,  G06F7/00 ,  G11C8/00

Abstract: The invention relates to two methods for reading and two methods for storing data, and also to an apparatus for compressing data and decompressing data which are provided for storage by a computer system 51 on a bulk memory 60 of the random access type, which computer system provides the data for storage on a bulk memory on the basis of the rules of a file system, where the data are organized in data blocks, where the data blocks contain organization information for managing the data blocks and contain the user information which is to be stored, where cohesive user information areas can be distributed over a plurality of data blocks which are then concatenated to one another using their organization information.

公开(公告)号：DE10051719C2

公开(公告)日：2003-10-02

申请号：DE10051719

申请日：2000-10-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KLING SABINE ,  SAVIGNAC DOMINIQUE ,  MOLL HANS-PETER ,  HAFFNER HENNING ,  HIETSCHOLD ELKE

IPC: H01L21/768 ,  H01L21/8242 ,  H01L23/528 ,  H01L27/02 ,  H01L27/105 ,  H01L21/312 ,  H01L21/8239 ,  H01L27/108

Abstract: The method involves using a lithographic process, whereby photo-lacquer structures are formed on the semiconducting substrate (5) to define dummy circuit structures. If an envisaged dummy structure (4) is smaller than a minimum size determined by the smallest required adhesive surface for photo-lacquer the first dummy structure is combined with a second to exceed the minimum size. An independent claim is also included for the following: a semiconducting substrate with functional circuit structures and dummy structures.

公开(公告)号：DE10121131C1

公开(公告)日：2002-12-19

申请号：DE10121131

申请日：2001-04-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BAENISCH ANDREAS ,  KLING SABINE

IPC: G11C11/4074 ,  G11C29/00

Abstract: A data memory for storing data, having a memory cell array (2), which comprises a large number of memory cells (3), each of which can be addressed by means of a memory cell select transistor (4) connected to a word line (9) and to a bit line (13) and which have a storage capacity for storing one data bit, the memory cell array (2) containing redundant memory cells (3'), which are provided in order to replace memory cells (3) which have been produced wrongly, by means of readdressing, and having read amplifiers (22), which are in each case provided for the signal amplification of a data bit read from an addressed memory cell (3) via an associated bit line (13) and are supplied with a buffered supply voltage, the redundant memory cells (3') which have not been readdressed being connected to the associated bit lines (13') and additionally buffering the supply voltage for the read amplifiers (22).