公开(公告)号：DE10323007A1

公开(公告)日：2004-12-30

申请号：DE10323007

申请日：2003-05-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BOTT NIKOLAUS ,  HAEBERLEN OLIVER ,  KOTEK MANFRED ,  LARIK JOOST ,  MAERZ JOSEF ,  OTREMBA RALF

IPC: H01L23/31 ,  H01L25/065 ,  H01L21/58 ,  H01L21/56 ,  H01L23/28

Abstract: The invention relates to a vertical arrangement of at least two semiconductor components which are electrically insulated from one another by at least one passivation layer. The invention likewise relates to a method for fabricating such a semiconductor arrangement. A semiconductor arrangement is specified in which, inter alia, the risk of cracking at the metallization edges, for example, caused by thermomechanical loading, is reduced and the fabrication-dictated high content of radical hydrogen is minimized. Furthermore, a method for fabricating such a semiconductor arrangement is specified.

公开(公告)号：DE10323007B4

公开(公告)日：2005-10-20

申请号：DE10323007

申请日：2003-05-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BOTT NIKOLAUS ,  HAEBERLEN OLIVER ,  KOTEK MANFRED ,  LARIK JOOST ,  MAERZ JOSEF ,  OTREMBA RALF

IPC: H01L23/31 ,  H01L25/065 ,  H01L21/58 ,  H01L21/56 ,  H01L23/28

Abstract: The invention relates to a vertical arrangement of at least two semiconductor components which are electrically insulated from one another by at least one passivation layer. The invention likewise relates to a method for fabricating such a semiconductor arrangement. A semiconductor arrangement is specified in which, inter alia, the risk of cracking at the metallization edges, for example, caused by thermomechanical loading, is reduced and the fabrication-dictated high content of radical hydrogen is minimized. Furthermore, a method for fabricating such a semiconductor arrangement is specified.