公开(公告)号：WO0227789B1

公开(公告)日：2002-07-25

申请号：PCT/DE0103439

申请日：2001-09-10

Applicant: INFINEON TECHNOLOGIES AG ,  BERGMANN ROBERT ,  LARIK JOOST ,  OTREMBA RALF ,  SCHLOEGEL XAVER ,  SCHREDL JUERGEN

Inventor： BERGMANN ROBERT ,  LARIK JOOST ,  OTREMBA RALF ,  SCHLOEGEL XAVER ,  SCHREDL JUERGEN

IPC: H01L23/482 ,  H01L23/495

CPC classification number: H01L24/48 ,  H01L23/49513 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/05556 ,  H01L2224/05599 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/73265 ,  H01L2224/83825 ,  H01L2224/85399 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01052 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/00

Abstract: The aim of the invention is to take up the smallest amount of space possible while effecting the thermomechanical release in tension at the junction between a circuit unit (2) and contact device (4) of a circuit (1), said junction being provided by means of the connecting device (10). To this end, the connecting device (10) is essentially provided as a prefabricated metallic or alloy region in the area of the circuit unit (2) and in the area of the contact device (4) while avoiding, to the greatest possible extent, the use of adhesive elements and solder elements.

Abstract translation: 为了占用在热机械浮雕尽可能少的空间用于电路单元（2）的与接触装置的连接（4）的电路布置（1）通过连接装置（10），根据建议的本发明，所述连接装置（10）基本上是金属的，并且预制 形式或合金区域中的电路单元（2）的区域中并且在所述接触装置（4），同时基本上避免粘附元件和焊料元件的区域中。

公开(公告)号：WO0101484A3

公开(公告)日：2001-08-16

申请号：PCT/DE0001772

申请日：2000-05-30

Applicant: INFINEON TECHNOLOGIES AG ,  LARIK JOOST ,  HIRLER FRANZ ,  KOTEK MANFRED ,  PFIRSCH FRANK

Inventor： LARIK JOOST ,  HIRLER FRANZ ,  KOTEK MANFRED ,  PFIRSCH FRANK

IPC: H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L29/36

CPC classification number: H01L29/1095 ,  H01L29/42368 ,  H01L29/7813

Abstract: The invention relates to a trench MOS-transistor, in which the body region (6) is strengthened by an implantation area (7) which faces the drain region (1, 2), in order to increase the avalanche resistance.

Abstract translation: 本发明涉及一种沟槽MOS晶体管，其中体区（6）被增强以通过注入区（7）增加雪崩电阻到漏极区（1,2）。

公开(公告)号：DE10127885B4

公开(公告)日：2009-09-24

申请号：DE10127885

申请日：2001-06-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ZUNDEL MARKUS ,  HIRLER FRANZ ,  LARIK JOOST ,  HENNINGER RALF ,  KOTEK MANFRED

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/739 ,  H01L29/78

Abstract: A trench power semiconductor component is described which has an edge cell in which an edge trench is provided. The edge trench, at least on an outer side wall, has a thicker insulating layer than an insulating layer of trenches of the cell array. This simple configuration provides a high dielectric strength and is economical to produce.

公开(公告)号：DE10124141B4

公开(公告)日：2009-11-26

申请号：DE10124141

申请日：2001-05-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BERGMANN ROBERT ,  LARIK JOOST ,  OTREMBA RALF ,  SCHLOEGEL XAVER ,  SCHREDL JUERGEN

IPC: H01L23/047 ,  H01L23/482 ,  H01L23/495 ,  H01L23/50

公开(公告)号：DE10323007A1

公开(公告)日：2004-12-30

申请号：DE10323007

申请日：2003-05-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BOTT NIKOLAUS ,  HAEBERLEN OLIVER ,  KOTEK MANFRED ,  LARIK JOOST ,  MAERZ JOSEF ,  OTREMBA RALF

IPC: H01L23/31 ,  H01L25/065 ,  H01L21/58 ,  H01L21/56 ,  H01L23/28

Abstract: The invention relates to a vertical arrangement of at least two semiconductor components which are electrically insulated from one another by at least one passivation layer. The invention likewise relates to a method for fabricating such a semiconductor arrangement. A semiconductor arrangement is specified in which, inter alia, the risk of cracking at the metallization edges, for example, caused by thermomechanical loading, is reduced and the fabrication-dictated high content of radical hydrogen is minimized. Furthermore, a method for fabricating such a semiconductor arrangement is specified.

公开(公告)号：DE50015742D1

公开(公告)日：2009-10-29

申请号：DE50015742

申请日：2000-05-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LARIK JOOST ,  HIRLER FRANZ ,  KOTEK MANFRED ,  PFIRSCH FRANK

IPC: H01L23/00 ,  H01L29/10 ,  H01L29/36 ,  H01L29/423 ,  H01L29/78

Abstract: A trench MOS-transistor includes a body region strengthened by an implantation area that faces the drain region to increase the avalanche resistance.

公开(公告)号：DE10124141A1

公开(公告)日：2002-04-11

申请号：DE10124141

申请日：2001-05-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BERGMANN ROBERT ,  LARIK JOOST ,  OTREMBA RALF ,  SCHLOEGEL XAVER ,  SCHREDL JUERGEN

IPC: H01L23/482 ,  H01L23/495 ,  H01L23/50

Abstract: The aim of the invention is to take up the smallest amount of space possible while effecting the thermomechanical release in tension at the junction between a circuit unit (2) and contact device (4) of a circuit (1), said junction being provided by means of the connecting device (10). To this end, the connecting device (10) is essentially provided as a prefabricated metallic or alloy region in the area of the circuit unit (2) and in the area of the contact device (4) while avoiding, to the greatest possible extent, the use of adhesive elements and solder elements.

公开(公告)号：DE50013469D1

公开(公告)日：2006-10-26

申请号：DE50013469

申请日：2000-05-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LARIK JOOST ,  HIRLER FRANZ ,  KOTEK MANFRED

IPC: H01L29/423 ,  H01L21/336 ,  H01L29/40 ,  H01L29/51 ,  H01L29/78

Abstract: A method for fabricating a trench MOS transistor includes the step of at least partly filling the trench with a conductive material which is isolated from the inner surface of the trench by an insulating layer. The insulating layer has a layer thickness that is larger in the region of the lower end of the trench than at the upper end of the trench.

公开(公告)号：DE10323007B4

公开(公告)日：2005-10-20

申请号：DE10323007

申请日：2003-05-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BOTT NIKOLAUS ,  HAEBERLEN OLIVER ,  KOTEK MANFRED ,  LARIK JOOST ,  MAERZ JOSEF ,  OTREMBA RALF

IPC: H01L23/31 ,  H01L25/065 ,  H01L21/58 ,  H01L21/56 ,  H01L23/28

Abstract: The invention relates to a vertical arrangement of at least two semiconductor components which are electrically insulated from one another by at least one passivation layer. The invention likewise relates to a method for fabricating such a semiconductor arrangement. A semiconductor arrangement is specified in which, inter alia, the risk of cracking at the metallization edges, for example, caused by thermomechanical loading, is reduced and the fabrication-dictated high content of radical hydrogen is minimized. Furthermore, a method for fabricating such a semiconductor arrangement is specified.

公开(公告)号：DE10127885A1

公开(公告)日：2002-12-19

申请号：DE10127885

申请日：2001-06-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ZUNDEL MARKUS ,  HIRLER FRANZ ,  LARIK JOOST ,  HENNINGER RALF ,  KOTEK MANFRED

IPC: H01L29/423 ,  H01L29/739 ,  H01L29/78 ,  H01L29/06

Abstract: A trench power semiconductor component is described which has an edge cell in which an edge trench is provided. The edge trench, at least on an outer side wall, has a thicker insulating layer than an insulating layer of trenches of the cell array. This simple configuration provides a high dielectric strength and is economical to produce.