公开(公告)号：JP2007300121A

公开(公告)日：2007-11-15

申请号：JP2007119711

申请日：2007-04-27

Applicant: Infineon Technologies Ag ,  インフィネオン テクノロジーズ アクチエンゲゼルシャフト

Inventor： BOTHE KRISTOF ,  DRUMMER BERNHARD ,  SCHINDLER WOLFGANG ,  WALSER MICHAEL

IPC: H01L23/12

CPC classification number: G06K19/07745 ,  H01L23/49827 ,  H01L23/49855 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48472 ,  H01L2224/48599 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/4911 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/85385 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/078 ,  H01L2924/181 ,  H01L2924/19042 ,  H01L2924/19107 ,  H01L2924/351 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012

Abstract: PROBLEM TO BE SOLVED: To provide a chip module and a chip card each of which is strong against mechanical and thermal stress and methods for manufacturing the chip module and the chip card. SOLUTION: The chip module is provided with a base material 1 having a chip upper surface 2 and a contact upper surface 3 formed on the opposite side of the chip upper surface 2, a chip 8 mounted on the chip upper surface 2 of the base material 1, a contact bank 4 formed on the contact upper surface 3 of the base material 1, and at least one passage 6 formed on the base material 1. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供各自对机械和热应力强的芯片模块和芯片卡以及用于制造芯片模块和芯片卡的方法。 解决方案：芯片模块设置有具有芯片上表面2和形成在芯片上表面2的相对侧上的接触上表面3的基材1，安装在芯片上表面2的芯片上表面2上的芯片8 基材1，形成在基材1的接触上表面3上的接触堤4和形成在基材1上的至少一个通道6。版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2007188489A

公开(公告)日：2007-07-26

申请号：JP2006342574

申请日：2006-12-20

Applicant: Infineon Technologies Ag ,  インフィネオン テクノロジーズ アクチエンゲゼルシャフト

Inventor： DRUMMER BERNHARD ,  PUESCHNER FRANK ,  WOLFGANG SCHINDLER

IPC: G06K19/077 ,  G06K19/07

CPC classification number: H01L23/49855 ,  G06K19/07745 ,  G06K19/07747 ,  H01L23/3121 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/4848 ,  H01L2224/48599 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/49171 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/85181 ,  H01L2224/85186 ,  H01L2224/85385 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2224/48247 ,  H01L2924/00012 ,  H01L2224/13099 ,  H01L2224/05599

Abstract: PROBLEM TO BE SOLVED: To prevent breakage of a sealant by interlayer peeling within a bonding hole. SOLUTION: A smart card module comprises a substrate having a substrate upper surface and a substrate lower surface, a contact array disposed on the substrate lower surface, and a conductor structure including a via, which is disposed on the substrate upper surface. The via is provided to extend through the substrate, and connected to the contact array. A chip having a connection contact part connected to the conductor structure is mounted by use of a means for mounting the chip on the substrate upper surface or on the conductor structure. A sealing part for sealing the chip is formed on the chip, at least a part of the conductor structure and the substrate upper surface. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：为了防止在接合孔内层间剥离导致密封剂破裂。 解决方案：智能卡模块包括具有基板上表面和基板下表面的基板，设置在基板下表面上的接触阵列以及设置在基板上表面上的通孔的导体结构。 通孔设置成延伸穿过基板，并连接到接触阵列。 通过使用将芯片安装在基板上表面或导体结构上的装置来安装具有连接到导体结构的连接接触部分的芯片。 用于密封芯片的密封部分形成在芯片上，导体结构的至少一部分和基板上表面上。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：DE102016110378A1

公开(公告)日：2017-12-07

申请号：DE102016110378

申请日：2016-06-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KOLLER ADOLF ,  DRUMMER BERNHARD

IPC: H01L21/30

Abstract: Es wird ein Verfahren zum Entfernen eines Verstärkungsrings von einem Wafer beschrieben. Das Verfahren umfasst ein Bilden einer ringförmigen Vertiefung in einer ersten Oberfläche des Wafers und ein Abtrennen des Verstärkungsrings aus einem Innenbereich des Wafers entlang der ringförmigen Vertiefung.

公开(公告)号：DE102005061345A1

公开(公告)日：2007-06-28

申请号：DE102005061345

申请日：2005-12-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： DRUMMER BERNHARD ,  SCHINDLER WOLFGANG ,  PUESCHNER FRANK

IPC: G06K19/077

Abstract: The module has contact arrays (4) arranged on a bottom surface (3) of a substrate (1) where the dimensions of the contact arrays conform to ISOstandard. Conductor structures (5) arranged on a top surface (2) of the substrate are connected to the contact arrays, which have through paths (6) in cutouts in the substrate. A chip (8) electrically conductively contacts the conductor structures. An encapsulation (10) covers the chip and a portion of the conductor structures and the top surface of the substrate.

公开(公告)号：DE102015100783A1

公开(公告)日：2016-07-21

申请号：DE102015100783

申请日：2015-01-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRUNNBAUER MARKUS ,  DRUMMER BERNHARD ,  KASPAR KORBINIAN ,  MACKH GUNTHER

IPC: H01L21/301

Abstract: Ein Verfahren zum Zertrennen eines Wafers kann Folgendes aufweisen: Bilden mehrerer aktiver Bereiche in einem Wafer, wobei jeder aktive Bereich mindestens eine elektronische Komponente aufweist, wobei sich die aktiven Bereiche von einer ersten Oberfläche des Wafers über eine bestimmte Höhe in den Wafer hinein erstrecken und durch Trennungsbereiche getrennt sind, wobei die Trennungsbereiche metallfrei sind, Bilden mindestens eines Grabens im Wafer durch Plasmaätzen in mindestens einem Trennungsbereich von der ersten Oberfläche des Wafers. Der mindestens eine Graben erstreckt sich weiter in den Wafer als die mehreren aktiven Bereiche hinein. Das Verfahren kann ferner das Bearbeiten eines überbleibenden Anteils des Wafers im Trennungsbereich aufweisen, damit der Wafer in einzelne Chips geteilt wird.

公开(公告)号：DE102006019925B4

公开(公告)日：2010-09-16

申请号：DE102006019925

申请日：2006-04-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WALSER MICHAEL ,  DRUMMER BERNHARD ,  SCHINDLER WOLFGANG ,  BOTHE KRISTOF

IPC: G06K19/077

公开(公告)号：DE102006019925A1

公开(公告)日：2007-10-31

申请号：DE102006019925

申请日：2006-04-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WALSER MICHAEL ,  DRUMMER BERNHARD ,  SCHINDLER WOLFGANG ,  BOTHE KRISTOF

IPC: G06K19/077

Abstract: The module has contact arrays (4) arranged on a bottom surface (3) of a substrate (1) where the dimensions of the contact arrays conform to ISOstandard. Conductor structures (5) arranged on a top surface (2) of the substrate are connected to the contact arrays, which have through paths (6) in cutouts in the substrate. A chip (8) electrically conductively contacts the conductor structures. An encapsulation (10) covers the chip and a portion of the conductor structures and the top surface of the substrate.