公开(公告)号：DE10203152C1

公开(公告)日：2003-10-23

申请号：DE10203152

申请日：2002-01-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHROEGMEIER PETER ,  DIETRICH STEFAN ,  ACHARYA PRAMOD ,  KIESER SABINE ,  GRAESSER URSULA ,  SCHNEIDER HELMUT ,  MARKERT MICHAEL

IPC: G11C8/08 ,  H01L27/108 ,  H01L27/105

Abstract: The memory device (100) has at least one memory module and associated word decoder block and at least one driver transistor pair (101a,101b), coupled to the word decoder block at their gates (104) in a ring structure (RDC). The sources (102) of the driver transistor pair lie outside the ring structure and have a common diffusion zone, the drains lying within the ring structure and coupled to at least one memory row selection line (106a,106b), adjacent selection lines coupled via a coupling transistor (105) receiving the same gate signal as the driver transistor pair.