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    VOLTAGE PUMP WITH THROW-IN CONTROL MECHANISM
    2.
    发明专利
    VOLTAGE PUMP WITH THROW-IN CONTROL MECHANISM 审中-公开

    公开(公告)号：JP2002186247A

    公开(公告)日：2002-06-28

    申请号：JP2001322789

    申请日：2001-10-19

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： DIETRICH STEFAN ,  HEYNE PATRICK ,  MARX THILO ,  SCHOENIGER SABINE ,  SOMMER MICHAEL ,  HEIN THOMAS ,  MARKERT MICHAEL ,  PARTSCH TORSTEN ,  SCHROEGMEIER PETER ,  WEIS CHRISTIAN

    IPC: H02M3/07

    Abstract: PROBLEM TO BE SOLVED: To provide a voltage pump with a throw-in control mechanism in which the operation is stable at the time of increasing supply voltage and the output voltage being pumped is prepared as quickly as possible. SOLUTION: The voltage pump 7 for generating an increased output voltage is provided with a throw-in control mechanism having a transistor 1 connected between a terminal 3 for introducing a supply voltage and a terminal 4 for taking out an increased output voltage. Upon starting operation of the voltage pump 7, the increased output voltage is interrupted from the supply voltage through the transistor 1. A switch 2 transfers the higher one of the output voltage or the supply voltage to a substrate terminal and a gate terminal of the transistor 1, respectively. The throw-in control mechanism allows standby at the early state of increased output voltage in the safety rising operation of the voltage pump 7 without requiring a significant circuit cost.

    INTEGRATED MEMORY
    3.
    发明专利
    INTEGRATED MEMORY 失效

    公开(公告)号：JP2001035162A

    公开(公告)日：2001-02-09

    申请号：JP2000190006

    申请日：2000-06-23

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： DIETRICH STEFAN ,  MUSA SAGLAM ,  SCHROEGEMEIER PETER ,  MARKERT MICHAEL ,  SCHOENIGER SABINE ,  WEIS CHRISTIAN

    IPC: G11C11/408 ,  G11C7/00 ,  G11C8/00 ,  G11C8/10 ,  G11C11/401

    Abstract: PROBLEM TO BE SOLVED: To obtain an activation time having an approximately same length with respect to a first selection line of first and second groups by providing the situation in which first and second address paths have first and second lines and first and second decoder circuits, the first decoder circuit decodes a supplied address faster than the second decoder circuit and the first line has a longer signal progressing time than the second line. SOLUTION: An address terminal ADR is connected to column selection lines CSL of first and second groups G1 and G2 through first and second address paths made up with first and second lines L1 and L2 and first and second decoder circuits DEC1 and DECK. The speed of the circuit DEC2 is slower than the speed of the circuit DEC1. By making the total length of the line L2 to be longer than the total length of the line L1, the signal progressing time of the line L1 becomes longer than the signal progressing time of the line L2 and the difference in the decoding time of the circuits DEC1 and DEC2 is compensated for.

    4.
    发明专利
    未知

    公开(公告)号：DE19929172B4

    公开(公告)日：2006-12-28

    申请号：DE19929172

    申请日：1999-06-25

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SCHROEGMEIER PETER ,  DIETRICH STEFAN ,  SCHOENIGER SABINE ,  WEIS CHRISTIAN ,  MARKERT MICHAEL ,  MUSA SAGLAM

    IPC: G11C8/00 ,  G11C11/408 ,  G11C7/00 ,  G11C8/10 ,  G11C11/401

    Abstract: The integrated memory has a first address path, via which the address terminals are connected to first selection lines of a first group and which has corresponding first lines and a first decoder circuit. In addition, the integrated memory has a second address path, via which the address terminals are connected to first selection lines of a second group and which has corresponding second lines and a second decoder circuit. The first decoder circuit is faster than the second decoder circuit. The first lines have a longer signal propagation time than the second lines.

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