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    IC INTEGRATED CIRCUIT
    1.
    发明专利
    IC INTEGRATED CIRCUIT 失效

    公开(公告)号：JP2001044812A

    公开(公告)日：2001-02-16

    申请号：JP2000191018

    申请日：2000-06-26

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： HEYNE PATRICK ,  HEIN THOMAS ,  PARTSCH TORSTEN ,  MARX THILO

    IPC: H03K5/135 ,  H03H11/26 ,  H03K5/00 ,  H03K5/13 ,  H03K5/133 ,  H03K5/15 ,  H03K17/687 ,  H03L7/081

    Abstract: PROBLEM TO BE SOLVED: To vary the phase deviation between an output clock and a first clock signal in a more precise step stage by executing the adjustment setting of the phase deviation between the output clock and the first clock signal by means of the change of two currents supplied from a current source. SOLUTION: An adjustable current source I supplies adjustable currents IE and IL, whose sum is substantially fixed with respect to various kinds of adjustment setting from output sides 10 and 20. The current source I is constituted to send out a control signal, on which the currents IE and IL depend to a control input side and to execute the adjustment setting with the currents. Trp 10, a circuit using first to eighth TrN1-N8 and an inverter INV output the output clock OUT. Thus, an integrated circuit is obtained, by which the phase deviation between the output clock OUT and the clock signals E and L can be varied in a more precise step state.

    CIRCUIT GENERATING A LOCAL OUTPUT CLOCK SIGNAL
    2.
    发明专利
    CIRCUIT GENERATING A LOCAL OUTPUT CLOCK SIGNAL 失效

    公开(公告)号：JP2001229675A

    公开(公告)日：2001-08-24

    申请号：JP2001020713

    申请日：2001-01-29

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： HEIN THOMAS ,  MARX THILO ,  HEYNE PATRICK ,  PARTSCH TORSTEN

    IPC: G11C11/407 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/409

    Abstract: PROBLEM TO BE SOLVED: To attain an optimum signal generating time by avoiding defect caused by a propagation time in a circuit generating a local output clock signal for controlling a point of time at which data is sent out from a sending out delay mechanism in an output side of a memory field to a data path. SOLUTION: For example, in a DDR-SDRAM memory chip, a highly accurate output clock signal is required for sending stored data to a data path at an appropriate point of time, such an output clock signal is generated by a symmetric circuit 1. This circuit generates an output clock signal in the minimum time by integrating a multiplexer to a pulse ratio compensating circuit consisting of two branches 2, 3 being symmetric to each other.

    VOLTAGE PUMP WITH THROW-IN CONTROL MECHANISM
    4.
    发明专利
    VOLTAGE PUMP WITH THROW-IN CONTROL MECHANISM 审中-公开

    公开(公告)号：JP2002186247A

    公开(公告)日：2002-06-28

    申请号：JP2001322789

    申请日：2001-10-19

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： DIETRICH STEFAN ,  HEYNE PATRICK ,  MARX THILO ,  SCHOENIGER SABINE ,  SOMMER MICHAEL ,  HEIN THOMAS ,  MARKERT MICHAEL ,  PARTSCH TORSTEN ,  SCHROEGMEIER PETER ,  WEIS CHRISTIAN

    IPC: H02M3/07

    Abstract: PROBLEM TO BE SOLVED: To provide a voltage pump with a throw-in control mechanism in which the operation is stable at the time of increasing supply voltage and the output voltage being pumped is prepared as quickly as possible. SOLUTION: The voltage pump 7 for generating an increased output voltage is provided with a throw-in control mechanism having a transistor 1 connected between a terminal 3 for introducing a supply voltage and a terminal 4 for taking out an increased output voltage. Upon starting operation of the voltage pump 7, the increased output voltage is interrupted from the supply voltage through the transistor 1. A switch 2 transfers the higher one of the output voltage or the supply voltage to a substrate terminal and a gate terminal of the transistor 1, respectively. The throw-in control mechanism allows standby at the early state of increased output voltage in the safety rising operation of the voltage pump 7 without requiring a significant circuit cost.

    DELAY CIRCUIT HAVING ADJUSTABLE DELAY
    7.
    发明申请
    DELAY CIRCUIT HAVING ADJUSTABLE DELAY 审中-公开
    延时可调延迟电路

    公开(公告)号：WO02052725A3

    公开(公告)日：2003-08-28

    申请号：PCT/DE0104311

    申请日：2001-11-15

    Applicant: INFINEON TECHNOLOGIES AG ,  HEIN THOMAS ,  HEYNE PATRICK ,  MARX THILO ,  PARTSCH TORSTEN

    Inventor： HEIN THOMAS ,  HEYNE PATRICK ,  MARX THILO ,  PARTSCH TORSTEN

    IPC: H03K5/13

    CPC classification number: H03K5/131 ,  H03K5/133

    Abstract: The invention relates to a delay circuit having adjustable delay. The delay circuit comprises a first block (1) and a second block (2) that is connected in outgoing circuit thereto. Said blocks each have a chain of delay elements (11 to 16, 21 to 26). A switch group (4, 5) is assigned to each block and enables output-side taps on the delay elements (11 to 16, 21 to 26) to be selected by means of switches (S1 to S6) in order to be able to select a desired delay time. In order to simultaneously control the switch (S6), which is connected to the output-side delay element (16) of the first block (1), and the switch (S6), which is connected to the input-side delay element (26) of the second block (2), the control inputs of these switches are connected to one another. This prevents the occurrence of disturbing pulses also in the event of high clock-pulse rates of clock signals (A) that can be applied to the delay elements on the input side. For this reason, the inventive delay circuit is suited especially for use in delay closed loops in DDR memory chips.

    Abstract translation: 有与由第一块（1）和一个第二nachgestalteten块（2），每一个具有的延迟歌曲链（11至16，21至26）表明可调延迟的延迟电路。 每个块具有与由开关装置（S1到S6）的延迟元件，其输出侧的抽头（11〜16，21〜26）相关联的开关组（4，5）是可选择的，以能够选择期望的延迟时间。 对于第一个块（1）连接的开关（S6）和第二块的输入侧的延迟元件（26）的输出侧的延迟元件（16）的同时致动（2）连接的开关（S6）是其控制输入端连接在一起。 以这种方式，甚至可以在输入侧的高时钟速率可以被放置抵靠延迟元件的时钟信号（A）来避免故障。 因此所描述的延迟电路特别适合用于在DDR存储器芯片延迟锁定环路中使用。

    8.
    发明专利
    未知

    公开(公告)号：DE102006015114A1

    公开(公告)日：2007-10-18

    申请号：DE102006015114

    申请日：2006-03-31

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： HEIN THOMAS

    IPC: G11C7/02

    Abstract: An integrated semiconductor memory with generation of data comprises a clock connection to apply a clock signal, a memory cell array with memory cells to store data of a first data record and a data generator circuit with a first input connection to apply the data of the first data record, with a first output connection to output data of a second data record, and with a second output connection to generate a first control signal. The data generator circuit includes an evaluation unit whose input is supplied with the first data record, the second data record and a second control signal, the second control signal being delayed by one clock period of the clock signal with respect to the first control signal. The data generator circuit is adapted to generate the data values of the data of the second data record in dependence on the evaluation of the data values of the first and second data record and the second control signal.

    9.
    发明专利
    未知

    公开(公告)号：DE59913808D1

    公开(公告)日：2006-10-12

    申请号：DE59913808

    申请日：1999-06-09

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SCHOENIGER SABINE ,  DIETRICH STEFAN DR ,  SCHROEGMEIER PETER ,  MARX THILO ,  HEIN THOMAS

    IPC: G11C7/00 ,  G11C11/409 ,  G11C7/06 ,  G11C7/10 ,  G11C11/4096

    Abstract: Integrated memory includes a pair of data lines (DL,/DL) which is connected via at least one difference amplifier (SA) to a bit-line pair (BL,/BL). Data in the form of difference signals is transmitted from the data line pair via the difference amplifier to the bit-line pair, and from there into storage or memory cells (M) connected thereto. A control unit (C) is used to adjust the first potential states on the data line pair which correspond to the difference signals of the data to be written into the storage or memory cells, and to adjust at least one second potential state on the data line pair, which does not correspond to any data to be written into the storage or memory cells. A two- input detector unit (D) is connected to the data line pair and conducts a given control function with occurrence of the second potential state of the data line pair.

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