公开(公告)号：JP2002221555A

公开(公告)日：2002-08-09

申请号：JP2001319485

申请日：2001-10-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： DIETRICH STEFAN ,  HEYNE PATRICK ,  MARX THILO ,  SCHOENIGER SABINE ,  SOMMER MICHAEL ,  HEIN THOMAS ,  MARKERT MICHAEL ,  PARTSCH TORSTEN ,  SCHROEGMEIER PETER ,  WEIS CHRISTIAN

IPC: G01R31/28 ,  G06F11/22 ,  G11C11/401 ,  G11C11/407 ,  G11C29/00 ,  G11C29/34 ,  H01L21/66 ,  H01L21/822 ,  H01L27/04

Abstract: PROBLEM TO BE SOLVED: To constitute so as to agree with a specification and to test an integrated circuit with a very little cost, and to test a lot of circuits requiring little external labor. SOLUTION: In order to prevent the plural integrated circuits to be driven during a test mode contrary to each other, an input terminal 10 connected already in any case to a channel of an automatic test device is connected to a circuit means 30. An output driver can be cut off depending on a control signal provided to the input terminal 10 by the circuit means 30. The circuit means 30 has a demultiplexer 31 and a multiplexer 32. The demultiplexer can be controlled by a test control signal TMRDIS generated additionally besides by a test control signal TMCOMP. Since the input terminal 10 is connected to the tester channel in any case during the test mode, an additional external cost is not required.

公开(公告)号：JP2002186247A

公开(公告)日：2002-06-28

申请号：JP2001322789

申请日：2001-10-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： DIETRICH STEFAN ,  HEYNE PATRICK ,  MARX THILO ,  SCHOENIGER SABINE ,  SOMMER MICHAEL ,  HEIN THOMAS ,  MARKERT MICHAEL ,  PARTSCH TORSTEN ,  SCHROEGMEIER PETER ,  WEIS CHRISTIAN

IPC: H02M3/07

Abstract: PROBLEM TO BE SOLVED: To provide a voltage pump with a throw-in control mechanism in which the operation is stable at the time of increasing supply voltage and the output voltage being pumped is prepared as quickly as possible. SOLUTION: The voltage pump 7 for generating an increased output voltage is provided with a throw-in control mechanism having a transistor 1 connected between a terminal 3 for introducing a supply voltage and a terminal 4 for taking out an increased output voltage. Upon starting operation of the voltage pump 7, the increased output voltage is interrupted from the supply voltage through the transistor 1. A switch 2 transfers the higher one of the output voltage or the supply voltage to a substrate terminal and a gate terminal of the transistor 1, respectively. The throw-in control mechanism allows standby at the early state of increased output voltage in the safety rising operation of the voltage pump 7 without requiring a significant circuit cost.

公开(公告)号：DE10233760B4

公开(公告)日：2007-05-03

申请号：DE10233760

申请日：2002-07-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SOMMER MICHAEL

IPC: H01L27/11 ,  H01L21/822 ,  H01L21/8239 ,  H01L21/8244 ,  H01L27/06 ,  H01L27/105

Abstract: A circuit structure has at least two etching trenches disposed at sidewalls of a silicon block left behind during the etching of the structure. The etching trenches are disposed at angles with respect to one another that are prescribed by the form of the silicon block left behind. Semiconductor layer structures which can interact with one another diagonally across are in each case accommodated in the etching trenches. In this case, the function of the entire circuit structure results from the interaction of the layer structures disposed in the various etching trenches.

公开(公告)号：DE102004013929B3

公开(公告)日：2005-08-11

申请号：DE102004013929

申请日：2004-03-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SOMMER MICHAEL ,  DICKMANN RORY

IPC: G06F1/10 ,  G11C7/10 ,  G11C11/4096

Abstract: Method for controlling the reading in of a data signal to an input (E) of an electric circuit in an input latch (2) under the control of a clock signal (CLK). The datum displayed by the data signal in the input latch is carried over with a clock signal. The cycle flank of the clock signal is temporally displaced dependent on the time delay between a signal flank of the input signal and the clock signal flank such that the time delay between the two lies within a defined time window. Input circuit for an electronic circuit with an input latch (2) for temporary storage of a data signal.

公开(公告)号：DE10260770A1

公开(公告)日：2004-07-15

申请号：DE10260770

申请日：2002-12-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SOMMER MICHAEL ,  ENDERS GERHARD

IPC: G11C11/404 ,  H01L21/334 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/108

Abstract: A memory cell comprises a trench capacitor with electrodes (9,11) and a dielectric layer (10) in the base with a vertical select transistor (TR) above this with a channel connecting electrode and a bit line (BL). The channel partly encloses the trench hole and the corresponding word line (WL) at least partly encloses the channel. Independent claims are also included for the following: (a) a memory cell arrangement as above;and (b) a production process for the above

公开(公告)号：DE10226057B3

公开(公告)日：2004-02-12

申请号：DE10226057

申请日：2002-06-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SOMMER MICHAEL ,  FISCHER HELMUT

IPC: G11C5/14 ,  G11C11/4074

公开(公告)号：DE10208249A1

公开(公告)日：2003-09-11

申请号：DE10208249

申请日：2002-02-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SOMMER MICHAEL ,  ENDERS GERHARD

IPC: H01L21/8242 ,  H01L27/02 ,  H01L27/108

公开(公告)号：DE10053425A1

公开(公告)日：2002-05-29

申请号：DE10053425

申请日：2000-10-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MARX THILO ,  HEYNE PATRICK ,  PARTSCH TORSTEN ,  HEIN THOMAS ,  SCHROEGMEIER PETER ,  DIETRICH STEFAN ,  SCHOENIGER SABINE ,  WEIS CHRISTIAN ,  SOMMER MICHAEL

IPC: G11C8/08 ,  G11C8/10 ,  G11C8/18 ,  G11C8/00 ,  G11C7/00 ,  G11C11/407

公开(公告)号：DE102011054035B4

公开(公告)日：2020-08-20

申请号：DE102011054035

申请日：2011-09-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BERGER RUDOLF ,  LEHNERT WOLFGANG ,  MAUDER ANTON ,  SCHULZE HANS-JOACHIM ,  FOERG RAIMUND ,  GRUBER HERMANN ,  RUHL GÜNTHER ,  KELLERMANN KARSTEN ,  SOMMER MICHAEL ,  ROTTMAIR CHRISTIAN ,  RUPP ROLAND

IPC: H01L21/30 ,  H01L21/265 ,  H01L21/304 ,  H01L21/306

Abstract: Verfahren zum Herstellen eines Verbundwafers, aufweisend:Bereitstellen eines monokristallinen Halbleiterwafers (10) mit einer ersten Seite (11) und einer gegenüber der ersten Seite (11) angeordneten zweiten Seite (12);Abscheiden einer Formmasse (35) aufweisend zumindest Kohlenstoffpulver und/oder Pech auf der zweiten Seite (12) des Halbleiterwafers (10); undTempern der abgeschiedenen Formmasse (35) zum Ausbilden eines an dem Halbleiterwafer angebrachten Graphitträgers (36).

公开(公告)号：FR2987168A1

公开(公告)日：2013-08-23

申请号：FR1300612

申请日：2013-03-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BERGER RUDOLF ,  GRUBER HERMANN ,  LEHNERT WOLFGANG ,  RUHL GUENTHER ,  FOERG RAIMUND ,  MAUDER ANTON ,  SCHULZE HANS JOACHIM ,  KELLERMANN KARSTEN ,  SOMMER MICHAEL ,  ROTTMAIR CHRISTIAN ,  RUPP ROLAND

IPC: H01L21/71 ,  H01L21/20 ,  H01L21/48 ,  H01L23/14

Abstract: Procédé de fabrication d'une tranche (13) composite, caractérisé en ce qu'on se procure une tranche de support comprenant une couche de graphite, on se procure une tranche (10) semiconductrice monocristalline ayant une première face (11) et une deuxième face (12) ; et on forme une couche de liaison sur au moins l'une de la première face (11) de la tranche semiconductrice et de la couche de graphite de la tranche de support.