3.
    发明专利
    未知

    公开(公告)号:DE10021865C2

    公开(公告)日:2002-08-01

    申请号:DE10021865

    申请日:2000-05-05

    Abstract: An electronic component includes a semiconductor chip and/or a test structure. The semiconductor chip includes a multi-layer coating having at least one interconnect layer, at least one insulation layer, and at least one planarization layer. A method of producing the component is also disclosed. Embedded adhesion regions are provided in the planarization layer, whereby the adhesion regions provide adhesion surfaces to the adjacent insulation layers.

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