公开(公告)号：WO0197285A2

公开(公告)日：2001-12-20

申请号：PCT/DE0101989

申请日：2001-05-28

Applicant: INFINEON TECHNOLOGIES AG ,  HACKE HANS JUERGEN ,  HUEBNER HOLGER ,  KOENIGER AXEL ,  SEITZ MAX GERHARD ,  TILGNER RAINER

Inventor： HACKE HANS-JUERGEN ,  HUEBNER HOLGER ,  KOENIGER AXEL ,  SEITZ MAX-GERHARD ,  TILGNER RAINER

IPC: H01L21/48 ,  H01L21/60 ,  H01L21/603 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/4985 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/81 ,  H01L2224/81801 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00

Abstract: The invention relates to an electronic component consisting of a housing (1) and a first substrate (2) which has at least one integrated circuit. Several contact surfaces (4) are distributed in an arbitrary manner on the surface of the first substrate (2). The surface of a second substrate (3), which forms a housing, is connected mechanically to the surface of the first substrate (2) by means of an insulating connecting layer (5). Said second substrate (3) has contact connection surfaces (6) which are in direct, electrically conductive contact with the contact surfaces (4) of the first substrate (2), in addition to external contact surfaces (9) positioned symmetrically that are connected in a conductive manner to the contact connection surfaces (6) by means of through contacts (8) in the second substrate (3).

Abstract translation: 本发明涉及一种壳体（1）的电子部件，并具有第一衬底（2）被至少一个集成电路，其中，多个接触表面（4）的所述第一衬底的表面上随机（2）被布置成分布和外壳形成第二 衬底（3）通过一绝缘粘结层（5）与所述第一基片（2）的表面的表面机械地连接，其中，所述第二衬底（3）具有接触垫（6）连接到所述第一基板的所述接触表面（4）（2 ）是平坦的，并且导电地连接到和对称布置外接触面（9），其（经由通过触点8）（在第2基板3）与所述接触垫（6）导电连接。

公开(公告)号：DE10021865C2

公开(公告)日：2002-08-01

申请号：DE10021865

申请日：2000-05-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ALPERN PETER ,  SAUERT WOLFGANG ,  HERZOG THOMAS ,  SCHAUER HEINZ ,  TILGNER RAINER

IPC: H01L21/66 ,  H01L21/768 ,  H01L23/544 ,  H01L21/316

Abstract: An electronic component includes a semiconductor chip and/or a test structure. The semiconductor chip includes a multi-layer coating having at least one interconnect layer, at least one insulation layer, and at least one planarization layer. A method of producing the component is also disclosed. Embedded adhesion regions are provided in the planarization layer, whereby the adhesion regions provide adhesion surfaces to the adjacent insulation layers.

公开(公告)号：DE10029269B4

公开(公告)日：2005-10-13

申请号：DE10029269

申请日：2000-06-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HACKE HANS-JUERGEN ,  HUEBNER HOLGER ,  KOENIGER AXEL ,  SEITZ MAX-GERHARD ,  TILGNER RAINER

IPC: H01L21/48 ,  H01L21/60 ,  H01L21/603 ,  H01L23/498 ,  H01L23/055 ,  H01L23/50

Abstract: Electronic component comprises a housing (1) and a first substrate (2) having at least one integrated circuit with contact surfaces (4) connected to electrodes of the parts of the component via conducting pathways. The contact surfaces are arranged on the surface of the first substrate, and a second substrate (3) forming a housing is connected to the surface of the first substrate via an insulating connecting layer (5). The second substrate has connecting surfaces (6) which are connected to the contact surfaces of the first substrate. The connecting surfaces (6) are connected via a wiring (7) insulated from the conducting pathways on the second substrate and via through-contacts (8) in the second substrate with symmetrically arranged outer contact surfaces (9) of the second substrate. An independent claim is also included for a process for the production of the electronic component. Preferred Features: The first substrate is a semiconductor wafer. The second substrate is a foil strip made from polyamide. The connecting surfaces are coated with a nickel and a gold layer.

公开(公告)号：DE10014308A1

公开(公告)日：2001-10-04

申请号：DE10014308

申请日：2000-03-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HACKE HANS-JUERGEN ,  HUEBNER HOLGER ,  KOENIGER AXEL ,  SEITZ MAX-GERHARD ,  TILGNER RAINER

IPC: H01L21/00 ,  H01L21/60 ,  H01L23/50

Abstract: Simultaneous multiple bonding between a semiconductor chip (4) and carrier (6) uses a heatable stamp (8) having projections (9) to fit the contacts. The contacts are coated with a low melting metal, which forms a higher melting solid phase with the contact after melting. A device for producing multiple bonding connections (1) between contact surfaces (2) on a semiconductor chip (4) and contact flags (5) of an intermediate carrier (6) comprises a heatable stamp (8) which simultaneously heats, presses and anneals the contacts and the pressure faces of projections (9) which are aligned to and fit the sizes of the contact faces. The contact surfaces have a low-melting metallic layer which forms higher melting point intermediate phases with the contact metals on melting. These phases solidify at a higher temperature than the low-melting material. An Independent claim also included for a process for multiple bonding connections as above.

公开(公告)号：DE102009031157A1

公开(公告)日：2010-07-01

申请号：DE102009031157

申请日：2009-06-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： NITSCH ALOIS ,  TILGNER RAINER ,  BAUMEISTER HORST

IPC: H01L21/66 ,  H01L23/544

Abstract: Ein Verfahren zum Erfassen eines Risses in einem Halbleiterwafer, der ein elektrisches Bauelement und eine Verbindungsanschlussfläche aufweist, die elektrisch mit dem elektrischen Bauelement gekoppelt ist, ist beschrieben. Der Riss wird durch einen Akustikdetektor erfasst, der akustisch mit dem Halbleiterwafer während des in Kontakt bringens der Kontaktierungsanschlussfläche mit einer Sonde gekoppelt ist.

公开(公告)号：DE10021865A1

公开(公告)日：2001-11-15

申请号：DE10021865

申请日：2000-05-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ALPERN PETER ,  SAUERT WOLFGANG ,  HERZOG THOMAS ,  SCHAUER HEINZ ,  TILGNER RAINER

IPC: H01L21/66 ,  H01L21/768 ,  H01L23/544 ,  H01L21/316

Abstract: A multilayer electronic component with a semiconductor chip (1) comprises conductive line (3,4,5), isolation (6-9) and planarizing layers (10), the last being a glass layer (11) with embedded adhesive regions (12) with adhesive faces (13,14) contacting neighboring isolation layers. Independent claims are also included for the following: (a) a component as above having a test structure; and (b) processes for making the component and test structure.

公开(公告)号：DE10014308B4

公开(公告)日：2009-02-19

申请号：DE10014308

申请日：2000-03-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HACKE HANS-JUERGEN ,  HUEBNER HOLGER ,  KOENIGER AXEL ,  SEITZ MAX-GERHARD ,  TILGNER RAINER

IPC: H01L21/603 ,  H01L21/00 ,  H01L23/50