公开(公告)号：JP2001351375A

公开(公告)日：2001-12-21

申请号：JP2001105822

申请日：2001-04-04

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HONIGSCHMID HEINZ ,  ROEHR THOMAS

IPC: G11C11/22 ,  H01L21/8246 ,  H01L27/105

Abstract: PROBLEM TO BE SOLVED: To reduce all standby current flowing during standby of a ferroelectric memory. SOLUTION: When a ferroelectric memory having a selection transistor, a memory cell, and a short circuit transistor is operated in a VDD/2 mode, the short circuit transistor is controlled during a standby period after read-out or write-in process controlled through word lines to which memory cells are arranged respectively and bit lines pre-charged in a pre-charge period, electrodes of an accumulation capacitor are short-circuited, a standby period is made temporally same as a pre-charge period, and bit lines have an another potential for both electrodes of accumulation potential.

公开(公告)号：JP2001351376A

公开(公告)日：2001-12-21

申请号：JP2001106108

申请日：2001-04-04

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ESTERL ROBERT ,  HONIGSCHMID HEINZ ,  KANDOLF HELMUT ,  ROEHR THOMAS

IPC: G11C11/22

Abstract: PROBLEM TO BE SOLVED: To provide an operation method for integrated memory in which attenuation or damage of information stored in a memory cell is prevented. SOLUTION: Colum lines and substrate lines connected to a selected memory cell have an initial potential before being accessed, and activate row lines connected to the selected memory cell during one access, thereby, switch a selection transistor of the selected memory cell to be in a conduction state, apply a potential being different from a potential of a column line to the substrate line, evaluate and amplify potentials applied to the column lines at a first point of time, successively, apply the initial potential to the substrate line at a second point of time, successively, apply the initial potential to column lines at a third point of time. The first point of time, the second point of time, and the third point of time are selected so that a memory capacitor of the selected memory cell is charged and discharged by the same quantity every time.

公开(公告)号：JP2001291386A

公开(公告)日：2001-10-19

申请号：JP2001047191

申请日：2001-02-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRAUN GEORG ,  HONIGSCHMID HEINZ

IPC: G11C11/22 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105

Abstract: PROBLEM TO BE SOLVED: To suppress occurrence of an error more than a publicly-known memory by providing an integrated memory. SOLUTION: This memory is provided with a driver unit, and a column selection line is connected to a plate type line segment through this driver unit, The driver unit forms a potential of a prescribed value for respective operation state of memories depending on a potential of a belonging column selection line and a word address of a connected plate type line segment.

公开(公告)号：JP2001283585A

公开(公告)日：2001-10-12

申请号：JP2001030127

申请日：2001-02-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ESTERL ROBERT ,  KANDOLF HELMUT ,  HONIGSCHMID HEINZ ,  ROEHR THOMAS

IPC: G11C11/22 ,  H01L21/8246 ,  H01L27/105

Abstract: PROBLEM TO BE SOLVED: To prevent change of memory contents caused by faulty voltage by connecting a column line and a charging line to a connection terminal 22 of a common power feeding potential GND in a non-active operation mode and in a common read-out amplifier or a driver circuit. SOLUTION: This integrated semiconductor memory is provided with a memory cell field having a ferroelectric memory effect memory cell MC, row lines WL1, and column lines BL1, the memory cell is inserted between one column line and a charging line PL1, the column line is connected to a read-out amplifier 2 from which an output signal S21 is taken, the charging line is connected to the driver circuit 3 connecting the amplifier 2 to a potential V1 and GND. and the column line and the charging line have an activation or a non-activation mode.