公开(公告)号：JP2002025248A

公开(公告)日：2002-01-25

申请号：JP2001195517

申请日：2001-06-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ESTERL ROBERT ,  MANYOKI ZOLTAN

IPC: G11C11/22 ,  G11C29/12

Abstract: PROBLEM TO BE SOLVED: To provide a simple circuit structure which corrects different voltages between respective line sections in a semiconductor integrated circuit, especially a circuit structure which corrects difference between the bit line voltage of a high level and the plate line voltage of a high level of a ferroelectric RAM memory and in which the different voltages (write voltage and read voltage in particular) are corrected with a standard operation and can mutually independently be decided in a test mode. SOLUTION: A voltage correction transistor is provided between a bit line and a plate line in order to solve the above problem.

公开(公告)号：JP2001307478A

公开(公告)日：2001-11-02

申请号：JP2001083633

申请日：2001-03-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BOEHM THOMAS ,  MANYOKI ZOLTAN ,  ESTERL ROBERT ,  ROEHR THOMAS

IPC: G11C11/22

Abstract: PROBLEM TO BE SOLVED: To improve accuracy of bit line reference voltage to read and write data in a memory capacitor MC in a memory in which a differential sense amplifier SA is connected to a pair of bit lines, for example, a ferroelectric memory to read and write data in a memory capacitor MC. SOLUTION: A main reference bit line/BL0 is connected to reference voltage VREF through a charging switch element TL. The other reference bit line/BLi is connected to the main bit line/BL0 through a balance adjusting switch element TA for electric charges balance adjustment between parasitic capacitance of each reference bit line. At the time, reference voltage VGEN is separated from the main reference bit line/BL0, other reference bit lines /BL1, /BL2, /BL3 are connected to the main reference bit line in parallel. Thereby, balance adjustment of electric charges accumulated in parasitic capacitance CPi of each reference bit line connected in parallel is performed, reference voltage VREF is distributed as equal plural bit line reference voltage V/BLi.

公开(公告)号：JP2000348485A

公开(公告)日：2000-12-15

申请号：JP2000143734

申请日：2000-05-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHLAGER TOBIAS ,  MANYOKI ZOLTAN ,  ESTERL ROBERT

IPC: G11C14/00 ,  G11C11/22 ,  G11C11/409 ,  G11C11/41

Abstract: PROBLEM TO BE SOLVED: To make generable a reference voltage in a comparatively short time by a method wherein a first switching element which is used to connect two bit lines and a selection transistor for two reference memory cells are turned on, only the selection transistor is turned off after a prescribed period, and the potential difference between the two bit lines is offset. SOLUTION: A first switching element S1 which short-circuits a first and second bit lines BL1 and the inverse of BL1, and a selection transistor for two reference memory cells RCs are turned on by a control unit C1. After a prescribed period has elaped, the first switching element S1 is continuously set to continuity, and the potential difference between the bit lines BL1 and the inverse of BL1 is offset. Consequently, the influence of the nonlinear memory capacitor of the reference memory cells RCs on a reference voltage is smaller than that, in a case where the selection transistor is set to continuity up to the perfect equilibrium of an electric charge between the bit lines BL1 and the inverse of BL1.

公开(公告)号：JP2001351376A

公开(公告)日：2001-12-21

申请号：JP2001106108

申请日：2001-04-04

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ESTERL ROBERT ,  HONIGSCHMID HEINZ ,  KANDOLF HELMUT ,  ROEHR THOMAS

IPC: G11C11/22

Abstract: PROBLEM TO BE SOLVED: To provide an operation method for integrated memory in which attenuation or damage of information stored in a memory cell is prevented. SOLUTION: Colum lines and substrate lines connected to a selected memory cell have an initial potential before being accessed, and activate row lines connected to the selected memory cell during one access, thereby, switch a selection transistor of the selected memory cell to be in a conduction state, apply a potential being different from a potential of a column line to the substrate line, evaluate and amplify potentials applied to the column lines at a first point of time, successively, apply the initial potential to the substrate line at a second point of time, successively, apply the initial potential to column lines at a third point of time. The first point of time, the second point of time, and the third point of time are selected so that a memory capacitor of the selected memory cell is charged and discharged by the same quantity every time.

公开(公告)号：JP2001283585A

公开(公告)日：2001-10-12

申请号：JP2001030127

申请日：2001-02-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ESTERL ROBERT ,  KANDOLF HELMUT ,  HONIGSCHMID HEINZ ,  ROEHR THOMAS

IPC: G11C11/22 ,  H01L21/8246 ,  H01L27/105

Abstract: PROBLEM TO BE SOLVED: To prevent change of memory contents caused by faulty voltage by connecting a column line and a charging line to a connection terminal 22 of a common power feeding potential GND in a non-active operation mode and in a common read-out amplifier or a driver circuit. SOLUTION: This integrated semiconductor memory is provided with a memory cell field having a ferroelectric memory effect memory cell MC, row lines WL1, and column lines BL1, the memory cell is inserted between one column line and a charging line PL1, the column line is connected to a read-out amplifier 2 from which an output signal S21 is taken, the charging line is connected to the driver circuit 3 connecting the amplifier 2 to a potential V1 and GND. and the column line and the charging line have an activation or a non-activation mode.

公开(公告)号：US6347059B2

公开(公告)日：2002-02-12

申请号：US81692501

申请日：2001-03-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BOEHM THOMAS ,  MANYOKI ZOLTAN ,  ESTERL ROBERT ,  ROEHR THOMAS

IPC: G11C11/22 ,  G11C7/02

CPC classification number: G11C11/22

Abstract: A semiconductor memory, in particular a ferroelectric semiconductor memory, has a differential write/read amplifier which is connected, via transfer transistors, to a bit line pair. The bit line pair includes a bit line and a corresponding reference bit line. The differential write/read amplifier is for reading data from and writing data to the memory capacitor (MC). In order to improve the accuracy of the bit line reference voltage, a main reference bit line is connected, via a charge switching element, to a reference voltage. At least one further reference bit line is connected to the main reference bit line via an equalization switching element for charge equalization between the reference bit lines.

Abstract translation: 半导体存储器，特别是铁电半导体存储器，具有通过传输晶体管连接到位线对的差分写/读放大器。 位线对包括位线和对应的参考位线。 差分写/读放大器用于从存储电容（MC）读取数据并将数据写入存储电容（MC）。 为了提高位线参考电压的精度，主参考位线经由充电开关元件连接到参考电压。 至少一个另外的参考位线通过用于参考位线之间的电荷均衡的均衡开关元件连接到主参考位线。

公开(公告)号：DE10017368B4

公开(公告)日：2005-12-15

申请号：DE10017368

申请日：2000-04-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ROEHR THOMAS ,  ESTERL ROBERT ,  HOENIGSCHMID HEINZ ,  KANDOLF HELMUT

IPC: G11C11/22 ,  G11C7/02 ,  G11C7/08 ,  G11C7/22

Abstract: A description is given of a method for operating an integrated memory which has memory cells each having a selection transistor and a storage capacitor with a ferroelectric storage effect. The memory contains a plate line, which is connected to one of the column lines via a series circuit containing a selection transistor and a storage capacitor of respective memory cells. A memory access is carried out according to the "pulsed plate concept". In this case, the temporal sequence is controlled in such a way that, in an access cycle, the storage capacitor of the memory cell to be selected is in each case charged and discharged by the same amount. An attenuation or destruction of the information stored in the memory cells, which is caused by source-drain leakage currents of unactivated selection transistors, is thus avoided.

公开(公告)号：DE10014385B4

公开(公告)日：2005-12-15

申请号：DE10014385

申请日：2000-03-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MANYOKI ZOLTAN ,  ESTERL ROBERT ,  BOEHM THOMAS ,  LAMMERS STEFAN

IPC: G05F3/24 ,  H01L23/58 ,  H01L27/085 ,  H03H11/00

公开(公告)号：DE10031947B4

公开(公告)日：2006-06-14

申请号：DE10031947

申请日：2000-06-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ESTERL ROBERT ,  MANYOKI ZOLTAN

IPC: G11C11/22 ,  G11C29/12 ,  G11C29/52 ,  H01L23/58 ,  H01L27/105

Abstract: The invention relates to a circuit configuration for equalizing different voltages on line runs in integrated semiconductor circuits, where the bit line and the plate line have a voltage equalization transistor provided between them which, in normal operation of the semiconductor circuit, can be switched to low impedance by a control signal in order to equalize the different voltages on the lines.

公开(公告)号：DE10017368A1

公开(公告)日：2001-10-11

申请号：DE10017368

申请日：2000-04-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ROEHR THOMAS ,  ESTERL ROBERT ,  HOENIGSCHMID HEINZ ,  KANDOLF HELMUT

IPC: G11C11/22

Abstract: The integrated memory device operating method uses a pulsed plate concept for accessing a selected memory cell (MC0) of the memory cell matrix during each access cycle, with initial potentials applied to the column line (BLt) and the plate line (PL) of a required memory cell prior to it being accessed by activation of the row line (WL0), for switching the memory cell selection transistor (T0). The potential applied to the plate line is pulsed so that the during the access cycle the memory capacitor of the selected memory cell is charged and discharged.