公开(公告)号：DE59509883D1

公开(公告)日：2002-01-10

申请号：DE59509883

申请日：1995-08-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MELZNER HANNO ,  KOHLHASE DR

IPC: G11C11/22 ,  G11C11/24 ,  G11C23/00

Abstract: The memory with a number of memory cells, such as a read-only (ROM) or dynamic random access (DRAM) memory and the like, is a miniaturised mechanical component. An initial insulation layer (2) is applied over the whole of the main surface of a carrier (1), to be covered over the whole surface by an electrically conductive membrane layer (3). The membrane layer (3) is structured to give the initial conductor paths (4) at the expanded sections (5) of the memory cells. The first insulation layer (2) is given an isotropic etching using the structured membrane layer (3) as the etching mask, until a sharp point (10) remains in the centre directly below the expansion (5). All the remaining material of the insulation layer (2) is removed at the under side of the expansion (5) to form the membrane (5). The membrane can be an oxidation of silicon for the required compressive stress.

公开(公告)号：DE59803426D1

公开(公告)日：2002-04-25

申请号：DE59803426

申请日：1998-12-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BOEHM THOMAS ,  OTANI DR ,  SCHLOESSER DR ,  WEINRICH DR ,  RUSCH ANDREAS ,  TRUEBY ALEXANDER ,  HAIN MANFRED ,  ZIMMERMANN DR ,  KOHLHASE DR

IPC: H01L21/8247 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

Abstract: The memory cell arrangement has several ferroelectric memory cells (S) provided in a semiconductor substrate (10). Parallel bit line grooves (1a-1e) run in the longitudinal direction in the main surface of the substrate. A bit line (15a-15d) is provided in the base of each groove. A source drain region (25a-25d) is provided at the ridge of each groove. A channel region is provided in the walls of each groove. The channel regions are provided in one groove wall, such that a controllable switching transistor for selecting the respective memory cell is formed, while the channel region in the other wall is arranged such that the respective transistor is off. Insulated word lines are provided in the transverse direction along the main surface of the substrate through the bit line grooves, to control the selection transistors. Insulation grooves (3a-3c) run in the transverse direction in the main surface of the substrate to insulate the source/drain regions of adjacent memory cells. A ferroelectric capacitor is connected to each source/drain region of respective memory cell (s) above the word lines (2a-2d).