公开(公告)号：DE59803426D1

公开(公告)日：2002-04-25

申请号：DE59803426

申请日：1998-12-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BOEHM THOMAS ,  OTANI DR ,  SCHLOESSER DR ,  WEINRICH DR ,  RUSCH ANDREAS ,  TRUEBY ALEXANDER ,  HAIN MANFRED ,  ZIMMERMANN DR ,  KOHLHASE DR

IPC: H01L21/8247 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

Abstract: The memory cell arrangement has several ferroelectric memory cells (S) provided in a semiconductor substrate (10). Parallel bit line grooves (1a-1e) run in the longitudinal direction in the main surface of the substrate. A bit line (15a-15d) is provided in the base of each groove. A source drain region (25a-25d) is provided at the ridge of each groove. A channel region is provided in the walls of each groove. The channel regions are provided in one groove wall, such that a controllable switching transistor for selecting the respective memory cell is formed, while the channel region in the other wall is arranged such that the respective transistor is off. Insulated word lines are provided in the transverse direction along the main surface of the substrate through the bit line grooves, to control the selection transistors. Insulation grooves (3a-3c) run in the transverse direction in the main surface of the substrate to insulate the source/drain regions of adjacent memory cells. A ferroelectric capacitor is connected to each source/drain region of respective memory cell (s) above the word lines (2a-2d).

公开(公告)号：DE59900872D1

公开(公告)日：2002-03-28

申请号：DE59900872

申请日：1999-09-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHLOESSER DR ,  HOFMANN DR ,  KRAUTSCHNEIDER PROF

IPC: H01L27/10 ,  H01L21/8242 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115

Abstract: A memory cell configuration with many ferroelectric or dynamic memory cells provided in a semiconductor substrate. Alternating trenches and lands extend parallel in a longitudinal direction of a main face of the semiconductor substrate. A channel stop layer is buried in the lands and divides the semiconductor substrate into a lower region that includes the trench bottoms and an upper region that includes the land ridges. First planar selection transistors with intervening trench channel stop regions are disposed along the trench bottoms. Second planar selection transistors with intervening land channel stop regions are disposed along the land ridges. The first and second selection transistors have respective source, gate, channel and drain regions, which are offset longitudinally from one another such that source and drain regions of the first and second selection transistors alternate in the transverse direction in the main face of the semiconductor substrate. Isolated word lines are provided which extend in the transverse direction along the main face for triggering the first and second selection transistors in the respective gate regions. Isolated bit lines are provided which extend in an oblique direction along the main face for connecting the first and second selection transistors in the respective source regions. And preferably ferroelectric capacitors are each connected to the drain regions of applicable selection transistors via capacitor contacts.