公开(公告)号：DE19815874C2

公开(公告)日：2002-06-13

申请号：DE19815874

申请日：1998-04-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： RUSCH ANDREAS ,  OTANI YOICHI ,  ROTHENHAEUSER STEFFEN ,  TRUEBY ALEXANDER ,  ZIMMERMANN ULRICH

IPC: H01L21/822 ,  H01L21/8246 ,  H01L27/04 ,  H01L27/10 ,  H01L27/112

Abstract: A method for fabricating a semiconductor memory device is described. An insulating layer is disposed on a semiconductor substrate. A matrix of semiconductor memory elements is disposed in the substrate. The semiconductor memory elements include a plurality of contact holes formed in the insulating layer. One contact hole is formed in the insulating layer for each of the semiconductor memory elements. A bit definition region is disposed in the semiconductor substrate underneath each of the contact holes. A contact plug is disposed in each of the contact holes and is in electrical contact with the bit definition region. The bit definition region is configured such that a contact resistance between the semiconductor substrate and the contact plug defines a bit to be stored in the semiconductor memory elements, An evaluation circuit is connected to and evaluates the contact resistance of the semiconductor memory elements.

公开(公告)号：DE102004014925B4

公开(公告)日：2016-12-29

申请号：DE102004014925

申请日：2004-03-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BARTH HANS-JOACHIM DR ,  SCHRÜFER KLAUS DR ,  RUSCH ANDREAS

IPC: H01L23/525

Abstract: Elektronische Schaltkreisanordnung mit einem Substrat, wobei das Substrat aufweist: mindestens eine Metallisierungsebene, in welcher ausgebildet sind mindestens eine elektrische Leitbahn (301), die an ihren Enden Kontaktbereiche (102, 202) aufweist und die in Mäander-Form als elektrische Schmelzsicherung ausgebildet ist, mehrere Durchkontaktierungen (304), die mit einem der Kontaktbereiche (102, 202) gekoppelt sind, und ein einzelnes Schmelzsicherungs-Kontaktloch (305), das als elektrische Schmelzsicherung ausgebildet ist und das mit dem anderen der Kontaktbereiche (102, 202) gekoppelt ist, und elektrische Schaltungskomponenten, die in einer Schaltungsebene unter der mindestens einen Metallisierungsebene angeordnet sind und die mittels der Durchkontaktierungen (304) und dem Schmelzsicherungs-Kontaktloch (305) mit der elektrischen Leitbahn (301) elektrisch gekoppelt sind.

公开(公告)号：DE59803426D1

公开(公告)日：2002-04-25

申请号：DE59803426

申请日：1998-12-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BOEHM THOMAS ,  OTANI DR ,  SCHLOESSER DR ,  WEINRICH DR ,  RUSCH ANDREAS ,  TRUEBY ALEXANDER ,  HAIN MANFRED ,  ZIMMERMANN DR ,  KOHLHASE DR

IPC: H01L21/8247 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

Abstract: The memory cell arrangement has several ferroelectric memory cells (S) provided in a semiconductor substrate (10). Parallel bit line grooves (1a-1e) run in the longitudinal direction in the main surface of the substrate. A bit line (15a-15d) is provided in the base of each groove. A source drain region (25a-25d) is provided at the ridge of each groove. A channel region is provided in the walls of each groove. The channel regions are provided in one groove wall, such that a controllable switching transistor for selecting the respective memory cell is formed, while the channel region in the other wall is arranged such that the respective transistor is off. Insulated word lines are provided in the transverse direction along the main surface of the substrate through the bit line grooves, to control the selection transistors. Insulation grooves (3a-3c) run in the transverse direction in the main surface of the substrate to insulate the source/drain regions of adjacent memory cells. A ferroelectric capacitor is connected to each source/drain region of respective memory cell (s) above the word lines (2a-2d).

公开(公告)号：DE19926499C2

公开(公告)日：2001-07-05

申请号：DE19926499

申请日：1999-06-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MOECKEL JENS ,  RUSCH ANDREAS

IPC: H01L23/525 ,  H01L23/532

公开(公告)号：DE59914831D1

公开(公告)日：2008-09-25

申请号：DE59914831

申请日：1999-03-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： RUSCH ANDREAS ,  ROTHENHAEUSSER STEFFEN ,  TRUEBY ALEXANDER ,  OTANI YOICHI ,  ZIMMERMANN ULRICH

IPC: H01L27/112 ,  H01L21/822 ,  H01L21/8246 ,  H01L27/04 ,  H01L27/10

Abstract: A method for fabricating a semiconductor memory device is described. An insulating layer is disposed on a semiconductor substrate. A matrix of semiconductor memory elements is disposed in the substrate. The semiconductor memory elements include a plurality of contact holes formed in the insulating layer. One contact hole is formed in the insulating layer for each of the semiconductor memory elements. A bit definition region is disposed in the semiconductor substrate underneath each of the contact holes. A contact plug is disposed in each of the contact holes and is in electrical contact with the bit definition region. The bit definition region is configured such that a contact resistance between the semiconductor substrate and the contact plug defines a bit to be stored in the semiconductor memory elements, An evaluation circuit is connected to and evaluates the contact resistance of the semiconductor memory elements.

公开(公告)号：DE102004014925A1

公开(公告)日：2005-10-13

申请号：DE102004014925

申请日：2004-03-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BARTH HANS-JOACHIM ,  SCHRUEFER KLAUS ,  RUSCH ANDREAS

IPC: H01L23/525

Abstract: An electronic circuit arrangement in accordance with some embodiments has a substrate, the substrate including: a plurality of metallization layers located one above the other; a single fuse-link via coupled between a first metallization layer and a second metallization layer of the plurality of metallization layers, wherein the single fuse-link via is in the form of an electrical fuse link preferentially programmable by applying a sufficiently large current to melt or degenerate the fuse link; a plurality of through-contact vias coupled in parallel between a third metallization layer and a fourth metallization layer of the plurality of metallization layers, wherein the through-contact vias form a through-contact between the third and fourth metallization layers; and electrical circuit components, arranged in a circuit layer, which are electrically coupled to one another by means of the single fuse-link via and by means of the plurality of through-contact vias.

公开(公告)号：DE19926499A1

公开(公告)日：2001-03-15

申请号：DE19926499

申请日：1999-06-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MOECKEL JENS ,  RUSCH ANDREAS

IPC: H01L23/525 ,  H01L23/532