公开(公告)号：JP2002134709A

公开(公告)日：2002-05-10

申请号：JP2001225140

申请日：2001-07-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOFFMANN KURT ,  KOWARIK OSKAR

IPC: G01R31/28 ,  G11C11/14 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/22 ,  H01L43/08

Abstract: PROBLEM TO BE SOLVED: To provide a method for nondestructively reading memory cell of MRAM memory which does not take up a large space or time for each read process. SOLUTION: Resistance RA.RP of a memory cell are not influenced by contents of the memory cell in a voltage region U1, while the resistances RA.RP vary according to the cell contents in another voltage region U2. Accordingly, the resistances RA.RP (U2) can be normalized by the resistances RA.RP (U1), in order to compare the contents of the memory cell which are different from each other. As a result, the normalized reading signal of a specified memory cell is compared with the normalized reference signal of a reference cell described by '0' or '1', and the contents of the memory cell as '1' or '0' can be detected.

公开(公告)号：JP2001160286A

公开(公告)日：2001-06-12

申请号：JP2000321401

申请日：2000-10-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOFFMANN KURT ,  KOWARIK OSKAR

IPC: G11C14/00 ,  G11C11/22

Abstract: PROBLEM TO BE SOLVED: To provide a device for self-reference for a ferroelectric memory cell which does not depend on the secular change of a memory cell and in which a hysteresis region is utilized as much as possible to obtain reference voltage. SOLUTION: While a bit line is pre-charged by two different voltage being the exact opposite each other having a first voltage value and a second voltage value, read-out can be performed in a memory cell, two voltage values obtained in this case are attained by enabling buffer to a first or a second capacitor respectively before these two voltage values are supplied to an evaluator to be compared.

公开(公告)号：WO0245090A3

公开(公告)日：2002-08-01

申请号：PCT/DE0104312

申请日：2001-11-16

Applicant: INFINEON TECHNOLOGIES AG ,  HOFFMANN KURT ,  KOWARIK OSKAR

Inventor： HOFFMANN KURT ,  KOWARIK OSKAR

IPC: G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08

CPC classification number: G11C11/16

Abstract: The invention relates to a circuit for the non-destructive, self-normalizing reading-out of MRAM memory cells. According to the invention, the read currents (Icell(0, 1)) of a memory cell are normalized by means of currents that are maintained at a voltage at which the size of these currents is independent of the cell content.

Abstract translation: 本发明涉及一种用于非破坏性的读出电流的读出MRAM存储单元的电路配置，selbstnormierenden（Izelle（0，1））通过的电流的装置的存储单元的归一化，这是在一个电压而获得的，其这些电流对细胞内容的大小是独立 ，

公开(公告)号：DE50106823D1

公开(公告)日：2005-08-25

申请号：DE50106823

申请日：2001-11-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOFFMANN KURT ,  KOWARIK OSKAR

IPC: G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08

Abstract: A circuit is provided for the non-destructive, self-normalizing reading-out of MRAM memory cells. Accordingly, read currents of a memory cell are normalized by currents that are maintained at a voltage at which the size of these currents is independent of the cell content. The circuit has a simple construction and without great expenditure, permits the normalization of a read signal.

公开(公告)号：DE59906886D1

公开(公告)日：2003-10-09

申请号：DE59906886

申请日：1999-03-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KOWARIK OSKAR ,  HOFFMANN KURT

IPC: G11C11/22 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/108

Abstract: A memory configuration includes a plurality of resistive ferroelectric memory cells. Each of the resistive ferroelectric memory cells includes a selection transistor and a storage capacitor. The selection transistor has a given zone of a first conductivity type. The storage capacitor has a first electrode and a second electrode. The first electrode is supplied with a fixed cell plate voltage. The second electrode is connected to the given zone of the first conductivity type. A semiconductor body of a second conductivity type opposite the first conductivity type is provided. A line is formed by a highly doped zone of the first conductivity type. The line is supplied with the cell plate voltage. The second electrode of the storage capacitor is connected via the resistor to the line.

公开(公告)号：DE59901953D1

公开(公告)日：2002-08-08

申请号：DE59901953

申请日：1999-09-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRAUN GEORG ,  HOENIGSCHMID HEINZ ,  ROEHR THOMAS ,  KOWARIK OSKAR ,  HOFFMANN KURT

IPC: G11C11/22 ,  G11C29/12

Abstract: A circuit for generating a reference voltage for the reading out from and the evaluation of read output signals which are read out with a constant plate voltage from storage cells of a ferroelectric memory via bit lines. In the circuit, a reference voltage device is formed of two reference cells that are subjected to the action of complementary signals. The reference cells can be simultaneously read out in order to generate the reference voltage in a selection and evaluation device.

公开(公告)号：DE19950581A1

公开(公告)日：2001-04-26

申请号：DE19950581

申请日：1999-10-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KOWARIK OSKAR ,  HOFFMANN KURT

IPC: G11C14/00 ,  G11C11/22

Abstract: The memory cell is read while the bit line (BL) is precharged to two different and opposite voltages (VCC, O V) at a first or a second voltage. The obtained voltage is buffered in a first or a second capacitance (CK1, CK2) before it is supplied to an evaluator (1). A cell plate line (CP) lies at a fixed supply voltage, or is subjected to a second or first voltage when the voltage at the first or second voltage is applied to the bit line.

公开(公告)号：DE10145556C2

公开(公告)日：2003-10-30

申请号：DE10145556

申请日：2001-09-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOFFMANN KURT ,  KOWARIK OSKAR

IPC: G11C29/00 ,  G11C7/06 ,  G11C11/4091 ,  H01L27/108

Abstract: An evaluation configuration has a first MOS evaluation stage, an isolation stage, and a bipolar evaluation stage. The isolation stage is connected between the first MOS evaluation stage and the bipolar evaluation stage. The isolation stage isolates the first MOS evaluation stage from the bipolar evaluation stage. The evaluation configuration can reliably detect very small read signals and allows a high integration density.

公开(公告)号：DE59903187D1

公开(公告)日：2002-11-28

申请号：DE59903187

申请日：1999-07-01

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KOWARIK OSKAR ,  HOFFMANN KURT

IPC: G11C11/22 ,  H01L21/8246 ,  H01L27/105

Abstract: A memory configuration includes a plurality of resistive ferroelectric memory cells. Each of the memory cells includes a selection transistor and a storage capacitor. The selection transistor has a given zone of a first conductivity type. The storage capacitor has a first and a second electrode. The first electrode is supplied with a fixed cell plate voltage, the second electrode is connected to the given zone of the first conductivity type. A source and a drain of a MOS transistor are supplied with the fixed cell plate voltage. The channel of the MOS transistor has a channel length extending over at least two of the memory cells. The given zone of the first conductivity type is connected, via a resistor, to the channel of the MOS transistor such that the given zone is electrically connected to the first electrode of the storage capacitor via the resistor and the MOS transistor.

公开(公告)号：DE10012105A1

公开(公告)日：2001-09-27

申请号：DE10012105

申请日：2000-03-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KOWARIK OSKAR ,  SCHULER FRANZ ,  SCHWERIN ANDREAS VON

IPC: G11C16/04 ,  G11C16/26 ,  H01L27/115

Abstract: The method involves determining a high and a low operating voltage depending on the state of charge of a floating gate (FG) of a transistor. A bias voltage is applied with blocking polarity between the bulk (B) and source (S) of the transistor during read-out.