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    SEMICONDUCTOR SUBSTRATE HOLDER AND MACHINE EQUIPPED WITH THE HOLDER FOR POLISHING THE SEMICONDUCTOR SUBSTRATE
    1.
    发明专利
    SEMICONDUCTOR SUBSTRATE HOLDER AND MACHINE EQUIPPED WITH THE HOLDER FOR POLISHING THE SEMICONDUCTOR SUBSTRATE 审中-公开

    公开(公告)号：JP2002359214A

    公开(公告)日：2002-12-13

    申请号：JP2002108468

    申请日：2002-04-10

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： HOLLATZ MARK ,  LAHNOR PETER

    IPC: B24B41/06 ,  H01L21/304 ,  B24B37/00 ,  B24B37/04

    Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor substrate holder which can uniformly polish the entire surface of a semiconductor substrate, and also to provide a machine equipped with the holder for polishing a semiconductor substrate. SOLUTION: A semiconductor substrate holder 20 has a movable plate mounted expandably inside a holder body 22. Polishing operation can be executed by a semiconductor substrate holder 20 in two fundamental processing modes, corresponding to two different end positions of the movable plate in a vertical direction. The plate 23 remains contacted mechanically with a substrate 12 in the first (lower direction) mode, air cushion is generated in a chamber 29 between the plate 23 for pressing the substrate 12 on a polishing pad 11 and the substrate 11 in the other second (upper direction) mode.

    3.
    发明专利
    未知

    公开(公告)号：DE10149916B4

    公开(公告)日：2007-01-25

    申请号：DE10149916

    申请日：2001-10-10

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： LAHNOR PETER ,  SIMPSON ALEXANDER

    IPC: H01L21/304 ,  H01L21/3105 ,  H01L21/762

    Abstract: Process for treating a structured process layer applied on a working surface in a semiconductor device comprises: applying an auxiliary layer on the process layer; and removing the filled process layer with a polishing device up to the working surface and planarizing the working surface. Process for treating a process layer (3') structured by a relief with recessed and raised sections (10, 11) and applied on a working surface (14) in a semiconductor device comprises: applying an auxiliary layer (4) on the process layer so that the recessed sections are partially filled with the auxiliary layer to form a filled process layer; and removing the filled process layer with a polishing device (15) up to the working surface and planarizing the working surface. Preferred Features: The working surface is tensioned in sections by surfaces of sections of a stop layer (2). The resistance or the solubility of the auxiliary layer can be adjusted. The auxiliary layer is made from spin on glass, organic polymers, doped silicon or silicones, and is applied using a spin on process or chemical vapor deposition (CVD).

    4.
    发明专利
    未知

    公开(公告)号：DE10157058A1

    公开(公告)日：2003-06-05

    申请号：DE10157058

    申请日：2001-11-21

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： LAHNOR PETER

    IPC: H01L21/768 ,  H01L23/544

    Abstract: A method and a semiconductor wafer configuration for producing an alignment mark for semiconductor wafers. In the method, an alignment mark region surrounded by a metal frame is formed on the semiconductor wafer. Subsequently, the alignment mark region and the metal frame are completely buried in at least one dielectric layer, in order to define an alignment mark area in the alignment mark region on the dielectric layer with a photolithography process. The boundary of the alignment mark area lies at a uniform distance within the boundary of the alignment mark region, defined by the metal frame. Subsequently (to uncover the alignment mark area by an anisotropic etching of the dielectric layer), the etching depth is defined in such a way that the alignment mark opening extends at least as far as the level of the metal frame.

    10.
    发明专利
    未知

    公开(公告)号：DE10042932C2

    公开(公告)日：2002-08-29

    申请号：DE10042932

    申请日：2000-08-31

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： LAHNOR PETER ,  WEGE STEPHAN

    IPC: H01L21/321 ,  H01L21/768 ,  H01L21/283

    Abstract: The optimization of a CMP process provides the use of an auxiliary layer (4) between a dielectric (1) in the vicinity of patterned portions and a layer of a liner (2). If the liner (2) is perforated in the CMP process, then the undercutting of the liner (2) by the chemical removal of the auxiliary layer (4) simplifies the process overall. Advantages are significantly lower defect densities due to CMP scratches, fewer short circuits, fewer alignment errors.

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