公开(公告)号：JP2002359214A

公开(公告)日：2002-12-13

申请号：JP2002108468

申请日：2002-04-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOLLATZ MARK ,  LAHNOR PETER

IPC: B24B41/06 ,  H01L21/304 ,  B24B37/00 ,  B24B37/04

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor substrate holder which can uniformly polish the entire surface of a semiconductor substrate, and also to provide a machine equipped with the holder for polishing a semiconductor substrate. SOLUTION: A semiconductor substrate holder 20 has a movable plate mounted expandably inside a holder body 22. Polishing operation can be executed by a semiconductor substrate holder 20 in two fundamental processing modes, corresponding to two different end positions of the movable plate in a vertical direction. The plate 23 remains contacted mechanically with a substrate 12 in the first (lower direction) mode, air cushion is generated in a chamber 29 between the plate 23 for pressing the substrate 12 on a polishing pad 11 and the substrate 11 in the other second (upper direction) mode.

公开(公告)号：DE102005002675B4

公开(公告)日：2007-02-22

申请号：DE102005002675

申请日：2005-01-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WELLHAUSEN UWE ,  HOLLATZ MARK ,  DAS ARABINDA ,  KLIPP ANDREAS ,  SPERLICH HANS-PETER ,  BIRNER ALBERT ,  HEIDEMEYER HENRY

IPC: H01L21/314 ,  H01L21/762

Abstract: The method involves pretreating a semiconductor structure before superimposing the spin-on layer to obtain a plane surface of the spin-on layer. A liner layer is superimposed on a semiconductor structure before the superimposition of the spin-on-layer. The semiconductor structure supports a planar superimposition of the spin-on layer on it. An oxide layer is superimposed as a liner layer, whose thickness is greater than 2.0 mm. An independent claim is also included for a semiconductor structure, in particular a semiconductor wafer with a substrate.

公开(公告)号：DE10314574A1

公开(公告)日：2004-10-28

申请号：DE10314574

申请日：2003-03-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MOTHES KERSTIN ,  KLIPP ANDREAS ,  SCHMITT FLORIAN ,  HOLLATZ MARK

IPC: H01L21/762

Abstract: Production of a shallow trench insulation structure comprises forming a mask (3) on a substrate (1), forming trenches (2) in the substrate using a mask, selectively depositing a first insulating material (5) to partially fill the trenches with the insulating material in the presence of the mask, and applying a second insulating material (6) on the whole surface of the structure to fill the trenches in the substrate up to the upper side of the mask.

公开(公告)号：DE10131668B4

公开(公告)日：2006-05-18

申请号：DE10131668

申请日：2001-06-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ROEMER ANDREAS ,  HOLLATZ MARK

IPC: H01L21/302 ,  B24B21/04 ,  B24B37/04 ,  B24B53/007

Abstract: A process is described for the chemical mechanical machining of semiconductor wafers. A plurality of surfaces are successively subjected to a polishing step, in which they are brought into contact with a polishing device. The polishing device contains a polishing-grain carrier with polishing grains, and the surfaces are moved relative to the polishing device. Material is removed from the surface by the polishing grains, which are fixed in the polishing-grain carrier and may become partially detached from the carrier material during the polishing operation. In each case one or more polishing steps is preceded by a conditioning step for regeneration of the polishing device. The polishing device and a conditioning surface of strong structure are brought into contact with one another and moved relative to one another, with the result that starting states of the polishing-device surface at a beginning of the individual polishing steps are comparable with one another.

公开(公告)号：DE10259322A1

公开(公告)日：2004-07-15

申请号：DE10259322

申请日：2002-12-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MOLL HANS-PETER ,  HOLLATZ MARK ,  MOTHES KERSTIN

IPC: G02B7/00 ,  G03F7/20 ,  G03F9/00

Abstract: Substrate comprises surface (91), first and second trenches (10, 20) of differing depth and width. First layer (50) is applied. Trench sizes and quantity applied ensure that smaller trench (20) is filled, but larger (10) is only partly filled. Second layer (30) is added which has greater etch selectivity compared with the first. Second layer thickness is adjusted during application, such that the first trench (10) is filled completely. The substrate is then chemically-mechanically polished, to lay bare the surface (91) of the substrate, and to form a planar surface over the first and second trenches. The second material is selectively etched to the first material, for partial opening (81) of the first trench, without using a resist- or resin mask. The opaque layer (100) is applied on the plane surface and into the opening (81) of the first trench (10) so that the alignment mark is formed as a depression (201) of the opaque layer, above the opening (81).

公开(公告)号：DE10120766C1

公开(公告)日：2002-10-02

申请号：DE10120766

申请日：2001-04-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ROEMER ANDREAS ,  HOLLATZ MARK ,  RADECKER JOERG

IPC: C23C16/04 ,  C23C16/507 ,  H01L21/3105 ,  H01L21/316 ,  H01L21/762 ,  C23C16/505 ,  C23F4/00 ,  H01L21/311

Abstract: Process for depositing a layer in a reactor (1) comprises feeding layer-forming gas, especially a sputtering gas, into the reactor; igniting a plasma (13) in the reactor; growing a layer on a deposition surface (14) by the plasma; partially removing the layer deposited on the deposition surface during a deposition process with simultaneous pure sputtering; removing non-horizontal surface regions of the deposited layer; and subjecting to pure sputtering. Preferred Features: The sputtering gas is a mixture of oxygen and argon. Silicon dioxide is deposited from silane gas. During the combined deposition and sputtering process and during the pure sputtering process, a pressure of 0.26-1.33 Pa prevails in the reactor.

公开(公告)号：DE10059345A1

公开(公告)日：2002-06-13

申请号：DE10059345

申请日：2000-11-29

Applicant: INFINEON TECHNOLOGIES AG ,  SPEEDFAM IPEC GMBH

Inventor： THIEME PETER ,  HOLLATZ MARK ,  REINHOLD FRANK ,  RIEMER KONSTANTIN

IPC: B24B37/30 ,  B24B37/32 ,  H01L21/3105 ,  H01L21/687 ,  H01L21/302 ,  B24B7/22 ,  B24B37/04 ,  H01L21/68

Abstract: The device has a base body (4) with a first main surface (9), a guide ring (7) attached to the base body and protruding above the main surface by a first height (11), a step (5) arranged laterally to the main surface next to the guide ring and protruding above the main surface by a second height (12) and a sealing film (6) arranged on the first main surface of the base body and on the step.

公开(公告)号：DE102004054285A1

公开(公告)日：2006-05-11

申请号：DE102004054285

申请日：2004-11-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MEYER FRANK CHRISTIAN ,  HOLLATZ MARK ,  VOGT MIRKO

IPC: H01L21/762

Abstract: Production of structures in a semiconductor substrate (1) comprises preparing a layer structure (12) with the substrate, applying an inert stop layer (11) on a first surface of the layer structure, etching trenches in the substrate from the side of the surface, completely filling the trenches with a dielectric (6), chemical-mechanical polishing a second surface until excess dielectric is removed from the stop layer and dissolving the stop layer from the first surface.

公开(公告)号：DE10131668A1

公开(公告)日：2003-01-30

申请号：DE10131668

申请日：2001-06-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ROEMER ANDREAS ,  HOLLATZ MARK

IPC: B24B21/04 ,  B24B37/04 ,  B24B53/007 ,  H01L21/302

Abstract: A process is described for the chemical mechanical machining of semiconductor wafers. A plurality of surfaces are successively subjected to a polishing step, in which they are brought into contact with a polishing device. The polishing device contains a polishing-grain carrier with polishing grains, and the surfaces are moved relative to the polishing device. Material is removed from the surface by the polishing grains, which are fixed in the polishing-grain carrier and may become partially detached from the carrier material during the polishing operation. In each case one or more polishing steps is preceded by a conditioning step for regeneration of the polishing device. The polishing device and a conditioning surface of strong structure are brought into contact with one another and moved relative to one another, with the result that starting states of the polishing-device surface at a beginning of the individual polishing steps are comparable with one another.

公开(公告)号：DE10123509A1

公开(公告)日：2002-11-28

申请号：DE10123509

申请日：2001-05-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOLLATZ MARK ,  TRUEBY ALEXANDER ,  TOEBBEN DIRK ,  MORHARD KLAUS-DIETER

IPC: H01L21/3105 ,  H01L21/762 ,  H01L21/8242

Abstract: The method involves applying a layer to be planarized over the semiconducting structure with recesses corresponding to trench regions. The substructures have a second sub-structure with second trench regions and the applied layer has further recesses above the second trench regions. A pre- planarizing mask masks a second area on the layer to be planarized above the second sub-structure.