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    ELECTRIC WIRING OF INTEGRATED CIRCUIT AND ITS MANUFACTURING METHOD
    1.
    发明专利
    ELECTRIC WIRING OF INTEGRATED CIRCUIT AND ITS MANUFACTURING METHOD 失效

    公开(公告)号：JP2001230505A

    公开(公告)日：2001-08-24

    申请号：JP2000379303

    申请日：2000-12-13

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： KIRCHHOFF MARKUS ,  ROGALLI MICHAEL ,  WEGE STEPHAN

    IPC: H05K1/03 ,  H01L21/283 ,  H01L21/312 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

    Abstract: PROBLEM TO BE SOLVED: To provide an electric wiring of an integrated circuit. SOLUTION: The electric wiring of the integrated circuit is provided with a substrate (1), conducting layer (2) which is arranged on the substrate (1) and structured to have a first conductor path (3), second conductor path (4) and a trench (5) between the first conductor path (3) and the second conductor path (4), and first dielectric layer (6) which is arranged on the conducting layer (2) and with which the trench (5) is at least partially filled. In this case, the first dielectric layer (6) contains one from among polybenzo-oxazole and/or polynorbornene and/or their derivatives, as the polymeric material.

    METHOD FOR PRODUCTION OF A SEMICONDUCTOR STRUCTURE
    3.
    发明申请
    METHOD FOR PRODUCTION OF A SEMICONDUCTOR STRUCTURE 审中-公开
    制造半导体结构的方法

    公开(公告)号：WO2004025714A3

    公开(公告)日：2004-05-13

    申请号：PCT/EP0309551

    申请日：2003-08-28

    Applicant: INFINEON TECHNOLOGIES AG ,  GENZ OLIVER ,  KIRCHHOFF MARKUS ,  MACHILL STEFAN ,  REB ALEXANDER ,  SCHMIDT BARBARA ,  STAVREV MOMTCHIL ,  STEGEMANN MAIK ,  WEGE STEPHAN

    Inventor： GENZ OLIVER ,  KIRCHHOFF MARKUS ,  MACHILL STEFAN ,  REB ALEXANDER ,  SCHMIDT BARBARA ,  STAVREV MOMTCHIL ,  STEGEMANN MAIK ,  WEGE STEPHAN

    IPC: H01L21/027 ,  H01L21/033 ,  H01L21/308 ,  H01L21/311 ,  H01L21/4763 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8244

    CPC classification number: H01L21/76811 ,  H01L21/0276 ,  H01L21/0332 ,  H01L21/3081 ,  H01L21/31144

    Abstract: The invention relates to a method for production of a semiconductor structure, comprising the steps: preparation of a semiconductor substrate (1), generation of a lower first, a middle second and an upper third masking layer (5, 7, 9) on a surface of the semiconductor substrate (1), formation of at least one first window (11, 11a-h) in the upper third masking layer (9), structuring the middle second masking layer (7) using the first window (11, 11a-h) in the upper third masking layer (9) for the transfer of the first window (11, 11a-h), structuring the lower first masking layer (5) using the first window (11, 11a-h) in the middle second masking layer (7) for the transfer of the first window (11, 11a-h), enlarging the first window (11, 11a-h) in the upper third masking layer (9) to form a second window (13, 13a-b) in a maskless process step, restructuring the middle second masking layer (7) using the second window (13, 13a-b) in the upper third masking layer (9) for the transfer of the second window (13, 13a-b), structuring the semiconductor substrate (1), using the structured lower third masking layer (5), restructuring the lower first masking layer (5) using the second window (13, 13a-b) in the middle second masking layer (7) and restructuring the semiconductor substrate (1) using the restructured lower third masking layer (5).

    Abstract translation: 本发明提供了一种半导体结构制造方法，包括以下步骤：提供半导体衬底（1）; 在所述半导体衬底（1）的表面上提供下第一掩膜层，中间第二掩膜层和上第三掩膜层（5,7,9）; 在所述上部第三掩模层（9）中形成至少第一窗口（11,11a-h）; 使用上部第三掩模层（9）中的第一窗口（11,11a-h）图案化中间第二掩模层（7）以传递第一窗口（11,11a-h）; 使用中间第二掩模层（7）中的第一窗口（11,11a-h）构造下部第一掩模层（5）以传送第一窗口（11,11a-h）; 扩大上部第三掩模层（9）中的第一窗口（11,11a-h）以在无掩模工艺步骤中形成第二窗口（13,13a-b）; 使用上部第三掩模层（9）中的第二窗口（13,13a-b）重构中央第二掩模层（7）以传送第二窗口（13,13a-b）; 使用图案化的下第三掩模层（5）图案化半导体衬底（1）; 使用中间第二掩模层（7）中的第二窗口（13,13a-b）重构下部第一掩模层（5）; 以及使用重构的下第三掩模层（5）重构半导体衬底（1）。

    4.
    发明专利
    未知

    公开(公告)号：DE50211481D1

    公开(公告)日：2008-02-14

    申请号：DE50211481

    申请日：2002-11-14

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： KIRCHHOFF MARKUS ,  VOGT MIRKO ,  WEGE STEPHAN ,  KATZWINKEL FRANK

    IPC: H01L21/033 ,  G03F7/09 ,  H01L21/027 ,  H01L21/308 ,  H01L21/31 ,  H01L21/311 ,  H01L21/312 ,  H01L21/3213 ,  H01L21/762 ,  H01L21/8242

    Abstract: Process for forming a structure in a semiconductor substrate (1) comprises producing an anti-reflective coating (2) on the semiconductor substrate and a buffer layer (3) on the anti-reflective coating layer, depositing a photoresist layer on the buffer layer, photolithographically producing a structure on the photoresist layer, and transferring this structure into the anti-reflective layer, buffer layer and semiconductor substrate arranged below the photoresist layer. An Independent claim is also included for the production of insulated regions between construction elements, especially trench capacitors, formed in a semiconductor substrate. Preferred Features: The buffer layer is a carbon layer or carbon-containing layer that is produced by a PECVD process. The anti-reflective layer consists of an organic substance or an SiO, SiON or SiN layer having a layer thickness less than 70 nm, especially about 45 nm.

    8.
    发明专利
    未知

    公开(公告)号：DE19944740C2

    公开(公告)日：2001-10-25

    申请号：DE19944740

    申请日：1999-09-17

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： KIRCHHOFF MARKUS ,  SPERLICH HANS-PETER ,  SCHILLING UWE ,  GABRIC ZVONIMIR ,  SPINDLER OSWALD ,  WEGE STEPHAN ,  GLAWISCHNIG HANS

    IPC: H01L21/316 ,  H01L21/318 ,  H01L21/762 ,  H01L21/314 ,  H01L21/768

    Abstract: A method for the shrink-hole-free filling of trenches in semiconductor circuits which utilizes selective growth of a layer to be applied is described. In the method, a layer of a selective growing material is applied simultaneously to a growth-promoting layer and to a growth-inhibiting layer. Wherein raised portions which, before the layer of selective growing material is applied, are covered by the growth-inhibiting layer at least on their sides. After the growth-inhibiting layer has been applied, the growth-promoting layer is generated by anisotropic treatment on surfaces parallel to the substrate on and between the raised portions and the layer is then removed again on surfaces parallel to the substrate on the raised portions. The method makes it possible to produce in a particularly simple manner a pattern on the raised portions of which are covered by the growth-inhibiting layer on their sides and on their top whereas the bottom of trenches is covered with a growth-promoting layer.

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