公开(公告)号：WO02056369A3

公开(公告)日：2003-03-20

申请号：PCT/EP0200102

申请日：2002-01-08

Applicant: INFINEON TECHNOLOGIES AG ,  GOLDBACH MATTHIAS ,  ORTH ANDREAS ,  LUETZEN JOERN

Inventor： GOLDBACH MATTHIAS ,  ORTH ANDREAS ,  LUETZEN JOERN

IPC: H01L27/108 ,  H01L21/20 ,  H01L21/8242

CPC classification number: H01L27/10867 ,  H01L27/1087

Abstract: A method for the production of trench capacitors, especially memory cells and at least one selection transistor for integrated semiconductor memories. According to the invention, the trench for the trench capacitor has a lower trench area (3-10c) in which the capacitor is arranged and an upper trench area (3-10a) in which an electrically conducting connection (3-44, 3-20b) between an electrode of the capacitor (3-20a) to a diffusion area of the selection transistor is disposed. The inventive method reduces the number of process steps for the production of memory cells and enables the production of buried shrouds in the memory capacitors which exhibit the same insulation quality as that which is required for the production of highly integrated memory cells (diameter

Abstract translation: 一种用于严重电容器，尤其是存储单元和用于集成半导体存储器中的至少一个选择晶体管的制备方法进行说明，其中所述沟槽为严重容量下部严重区域（3-10C），其中，所述电容器被布置和上严重区域（3-10C ），其中通过所述电容器（3-20a）的电极的导电性连接（3-44，3-20b）被布置以形成选择晶体管的扩散区域，其包括 这种方法减少了对存储单元的制造工艺步骤的数量，并且使生产掩埋套环在具有绝缘质量的存储电容器，作为用于生产（<300nm的严重直径）是必需的高度集成的存储器单元。

公开(公告)号：DE102005024855A8

公开(公告)日：2007-03-08

申请号：DE102005024855

申请日：2005-05-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： JAKSCHIK STEFAN ,  AVELLAN ALEJANDRO ,  SCHROEDER UWE ,  ORTH ANDREAS ,  GOLDBACH MATTHIAS ,  STORBECK OLAF ,  STADTMUELLER MICHAEL ,  HECHT THOMAS

IPC: H01L21/8242

Abstract: Memory and method for fabricating it A memory formed as an integrated circuit in a semiconductor substrate and having storage capacitors and switching transistors. The storage capacitors are formed in the semiconductor substrate in a trench and have an outer electrode layer, which is formed around the trench, a dielectric intermediate layer, which is embodied on the trench wall, and an inner electrode layer, with which the trench is essentially filled, and the switching transistors are formed in the semiconductor substrate in a surface region and have a first source/drain doping region, a second source/drain doping region and an intervening channel, which is separated from a gate electrode by an insulator layer.

公开(公告)号：DE102004002242A1

公开(公告)日：2005-08-11

申请号：DE102004002242

申请日：2004-01-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HECHT THOMAS ,  FOERSTER MATTHIAS ,  BIRNER ALBERT ,  ORTH ANDREAS ,  STADTMUELLER MICHAEL

IPC: H01L21/8239 ,  H01L21/334 ,  H01L21/8229 ,  H01L21/8242 ,  H01L29/94

Abstract: The invention provides a method for fabricating a memory cell, a substrate ( 101 ) being provided, a trench-type depression ( 102 ) being etched into the substrate ( 101 ), a barrier layer ( 103 ) being deposited non-conformally in the trench-type depression ( 102 ), grain elements ( 104 ) being grown on the inner areas of the trench-type depression ( 102 ), a dielectric layer ( 202 ) being deposited on the surfaces of the grain elements and the inner areas of the trench-type depression, and a conduction layer being deposited on the dielectric layer, the grain elements ( 104 ) growing selectively on the inner areas ( 105 ) of the trench-type depression ( 102 ) in an electrode region ( 301 ) forming a lower region of the trench-type depression ( 102 ) and an amorphous silicon layer continuing to grow in a collar region ( 302 ) forming an upper region of the trench-type depression ( 102 ).

公开(公告)号：DE102006013245A1

公开(公告)日：2007-10-04

申请号：DE102006013245

申请日：2006-03-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LAHNOR PETER ,  WUNNICKE ODO ,  HEITMANN JOHANNES ,  MOLL PETER ,  ORTH ANDREAS

IPC: H01L21/8242

Abstract: The method involves providing a substrate (1) with a substrate upper surface (10) with two surface sections (11, 12). A vertical columnar template is brought from a self-organized pattern material into the surface section (11). A mold layer is formed on the surface section (12) after forming the columnar template. The columnar template is removed after applying the mold layer, where an opening is formed in the mold layer via the surface section (11) of the substrate. Independent claims are also included for the following: (1) a method for manufacturing a contact structure (2) a method for manufacturing condensers in a substrate.

公开(公告)号：DE102005024855A1

公开(公告)日：2006-12-07

申请号：DE102005024855

申请日：2005-05-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： JASCHIK STEFAN ,  AVELLAN ALEJANDRO ,  SCHROEDER UWE ,  ORTH ANDREAS ,  GOLDBACH MATTHIAS ,  STORBECK OLAF ,  STADTMUELLER MICHAEL ,  HECHT THOMAS

IPC: H01L21/8242

Abstract: Memory and method for fabricating it A memory formed as an integrated circuit in a semiconductor substrate and having storage capacitors and switching transistors. The storage capacitors are formed in the semiconductor substrate in a trench and have an outer electrode layer, which is formed around the trench, a dielectric intermediate layer, which is embodied on the trench wall, and an inner electrode layer, with which the trench is essentially filled, and the switching transistors are formed in the semiconductor substrate in a surface region and have a first source/drain doping region, a second source/drain doping region and an intervening channel, which is separated from a gate electrode by an insulator layer.

公开(公告)号：DE102005044142B3

公开(公告)日：2007-03-01

申请号：DE102005044142

申请日：2005-09-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： RONGEN STEFAN ,  WURSTER KAI ,  ORTH ANDREAS ,  HAUPT MORITZ

IPC: H01L21/822 ,  H01L27/08

Abstract: A production process for an electrically conductive filling (30) in a trench in a semiconductor substrate (10) or layer comprises preparing the substrate and trench, depositing amorphous or polycrystalline silicon and phosphorus simultaneously in the trench and then forming at least one monolayer of arsenic atoms on the silicon/phosphorus interface. An independent claim is also included for a trench capacitor in a semiconductor substrate as above.

公开(公告)号：DE10319843A1

公开(公告)日：2004-12-02

申请号：DE10319843

申请日：2003-05-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HECHT THOMAS ,  SCHROEDER UWE ,  MANTZ ULRICH ,  JAKSCHIK STEFAN ,  ORTH ANDREAS

IPC: G01B11/22 ,  G01J3/453 ,  G01N21/21 ,  G01J1/20 ,  H01L21/66

Abstract: The blind bores depth measurement system uses interference effects. It has an IR source sending radiation (S) to a Michelson interferometer (10) with a beam splitter (13) at a 45 degree angle and two mirrors (11,12). The IR leaving the Michelson interferometer passes through a polarizer (21) and impinges on the workpiece (1) at a 45 degree angle. IR reflected from the workpiece passes through a second polarizer (22) to an IR detector (15).

公开(公告)号：DE10234952B3

公开(公告)日：2004-04-01

申请号：DE10234952

申请日：2002-07-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BIRNER ALBERT ,  GOLDBACH MATTHIAS ,  LUETZEN JOERN ,  ORTH ANDREAS ,  MANGER DIRK ,  KUDELKA STEPHAN ,  HECHT THOMAS ,  HEINECK LARS

IPC: H01L27/108 ,  H01L21/00 ,  H01L21/20 ,  H01L21/334 ,  H01L21/8242 ,  H01L29/94

Abstract: Production of a semiconductor structure comprises preparing a semiconductor substrate (1), forming a trench (5) in the substrate, filling the trench with a liquid filling material or a dissolvable material, hardening the filling material, removing the filling material from the upper region of the trench up to the boundary surface to define a collar region (15), providing a liner (30) in the collar region, penetrating the liner at the boundary surface to the filling material, and removing the filling material from the lower region of the trench.