公开(公告)号：WO0106542A3

公开(公告)日：2001-07-19

申请号：PCT/DE0002316

申请日：2000-07-17

Applicant: INFINEON TECHNOLOGIES AG ,  SCHULZ THOMAS ,  ROESNER WOLFGANG ,  FRANOSCH MARTIN ,  SCHAEFER HERBERT ,  RISCH LOTHAR ,  AEUGLE THOMAS

Inventor： SCHULZ THOMAS ,  ROESNER WOLFGANG ,  FRANOSCH MARTIN ,  SCHAEFER HERBERT ,  RISCH LOTHAR ,  AEUGLE THOMAS

IPC: H01L21/335 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/76 ,  H01L51/00 ,  H01L51/05 ,  H01L51/30

CPC classification number: B82Y10/00 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/7613 ,  H01L51/0048 ,  H01L51/0052 ,  H01L51/0512

Abstract: According to the invention, a double gate MOSFET semiconductor layer structure is formed on a substrate (1). This structure is comprised of a first and of a second gate electrode (10A, 10B) between which a semiconductor channel layer zone (4A) is embedded, and of a source region (2A) and a drain region (2B) which are arranged on opposite faces of the semiconductor channel layer zone (4A). At least one additional semiconductor channel layer zone (6A) is provided on one of the gate electrodes (10B). The faces of the at least one additional semiconductor channel layer zone are also contacted by the source region (2A) and drain region (2B).

Abstract translation: 在衬底（1）上构建双栅MOSFET半导体层结构。 这在半导体沟道层区的相对的端面由第一和在其之间的半导体沟道层区域（4A）被嵌入第二栅电极（10A，10B），以及源极（2A）和漏极区域（2b）中的 （4A）被布置。 在其中一个栅电极（10B）上提供至少一个另外的半导体沟道层区域（6A），其端面同样与源极（2A）和漏极区域（2B）接触。

公开(公告)号：WO0137342A2

公开(公告)日：2001-05-25

申请号：PCT/DE0003982

申请日：2000-11-14

Applicant: INFINEON TECHNOLOGIES AG ,  HOFMANN FRANZ ,  RISCH LOTHAR ,  ROESNER WOLFGANG ,  SCHLOESSER TILL

Inventor： HOFMANN FRANZ ,  RISCH LOTHAR ,  ROESNER WOLFGANG ,  SCHLOESSER TILL

IPC: H01L21/336 ,  H01L21/8242 ,  H01L27/108 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786 ,  H01L25/00

CPC classification number: H01L27/10864 ,  H01L27/10867 ,  H01L27/10891 ,  H01L27/1203

Abstract: The invention relates to a transistor that is provided with a first source/drain area (S/D1), a channel area (KA) adjacent thereto, a second source/drain area (S/D 2) adjacent thereto, a gate dielectric and a gate electrode. A first capacitor electrode (SP) of the capacitor is connected to the first source/drain area (S/D1). An insulating structure entirely surrounds an insulating area of the circuit arrangement. At least the first capacitor electrode (SP) and the first source/drain area (S/D1) are arranged in the insulating area. The second source/drain area (S/D2) and the second capacitor electrode of the capacitor are arranged outside the insulating area. The insulating structure prevents the first capacitor electrode (SP) from loosing charge through leaking currents between charging and discharging of the capacitor. A tunnel barrier (T) which is arranged in the channel area (KA) is part of the insulating structure. A capacitor dielectric (KD) that separates the first capacitor electrode (SP) from the second capacitor electrode is part of the insulating structure.

Abstract translation: 该晶体管的第一源极/漏极区（S / D1），其上的沟道区相邻的（KA），一个与其相邻的第二源极/漏极区（S / D2），栅极电介质和栅极电极。 所述电容器的第一电容器电极（SP）被连接到所述第一源极/漏极区（S / D1）。 绝缘结构完全围绕的电路的绝缘区域。 在至少所述第一电容器电极（SP）和所述第一源极的绝缘区/漏极区（S / D1）被布置，而第二源极/漏极区（S / D2）和所述电容器的第二电容器电极上的绝缘外 排列区域。 因为绝缘结构的电荷不会丢失由于从充电和放电电容器之间的第一电容器电极（SP）的漏电流。 在沟道区中的隧穿势垒（T），其设置（KA），是在绝缘结构的部分。 电容器电介质（KD），（SP）分离所述第二电容器电极的第一电容器电极，在绝缘结构的部分。

公开(公告)号：WO0243109A2

公开(公告)日：2002-05-30

申请号：PCT/DE0104358

申请日：2001-11-21

Applicant: INFINEON TECHNOLOGIES AG ,  HOFMANN FRANZ ,  RISCH LOTHAR ,  ROESNER WOLFGANG

Inventor： HOFMANN FRANZ ,  RISCH LOTHAR ,  ROESNER WOLFGANG

IPC: H01L21/336 ,  H01L29/08 ,  H01L29/78 ,  H01L29/786 ,  H01L

CPC classification number: H01L29/66643 ,  H01L29/0895 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/78654

Abstract: The invention relates to a planar field effect transistor comprising a barrier layer that lies adjacent to and/or below part of the gate region. Said barrier layer is configured between the source region and the channel region and/or between the drain region and the channel region in such a way that there is practically no diffusion of the doping atoms from the source region and the drain region into the channel region, but that electric charge carriers can tunnel through the barrier layer.

Abstract translation: 一种平面场效应晶体管具有邻近所述栅极区和/或之下的栅极区域的一部分的阻挡层，其中所述源极区和沟道区之间的势垒层/或漏极区和沟道区之间的被配置为使得 基本上没有掺杂剂原子的扩散是存在于源区和漏区可在沟道区中进行，但电荷载流子隧穿可以通过将阻挡层。

公开(公告)号：DE59813458D1

公开(公告)日：2006-05-11

申请号：DE59813458

申请日：1998-04-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KRAUTSCHNEIDER WOLFGANG ,  HOFMANN FRANZ ,  RISCH LOTHAR

IPC: H01L21/8238 ,  H01L27/092

Abstract: An integrated CMOS circuit arrangement and a method of manufacturing same, which includes both a first MOS transistor and a second MOS transistor complementary thereto, wherein one of the MOS transistors is arranged at the floor of a trench and the other is arranged at the principal surface of a semiconductor substrate. The MOS transistors are arranged relative to one another such that a current flow through the MOS transistors respectively occurs substantially parallel to a sidewall of the trench that is arranged between the MOS transistors.

公开(公告)号：DE50011071D1

公开(公告)日：2005-10-06

申请号：DE50011071

申请日：2000-06-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ROESNER WOLFGANG ,  SCHULZ THOMAS ,  RISCH LOTHAR ,  FRANOSCH MARTIN

IPC: H01L21/336 ,  H01L29/786

公开(公告)号：DE19524478C2

公开(公告)日：2002-03-14

申请号：DE19524478

申请日：1995-07-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOFMANN FRANZ ,  ROESNER WOLFGANG ,  KRAUTSCHNEIDER WOLFGANG ,  RISCH LOTHAR

IPC: H01L21/8247 ,  H01L27/115 ,  H01L27/11517 ,  H01L29/788 ,  H01L29/792

Abstract: PCT No. PCT/DE96/01117 Sec. 371 Date Dec. 8, 1997 Sec. 102(e) Date Dec. 8, 1997 PCT Filed Jun. 25, 1996 PCT Pub. No. WO97/02599 PCT Pub. Date Jan. 23, 1997An electrically writable and erasable read-only memory cell arrangement fabricated in a semiconductor substrate, preferably of monocrystalline silicon, or in a silicon layer of an SOI substrate. A cell array with memory cells is provided on a main surface of the semiconductor substrate. Each memory cell comprises an MOS transistor, vertical to the main surface and comprising, in addition to the source/drain region and a channel region arranged in-between, a first dielectric, a floating gate, a second dielectric and a control gate. A plurality of essentially parallel strip-shaped trenches are provided in the cell array. The vertical MOS transistors are arranged on the flanks of the trenches. The memory cells are in each case arranged on opposite flanks of the trenches.

公开(公告)号：DE19942692B4

公开(公告)日：2007-04-12

申请号：DE19942692

申请日：1999-09-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHULZ THOMAS ,  ROESNER WOLFGANG ,  RISCH LOTHAR

IPC: H01L27/14 ,  H01L31/0232 ,  G02B6/42 ,  H01L27/144 ,  H01L27/15 ,  H01L31/10 ,  H01L31/102

Abstract: In an integrated optoelectronic microelectronic system, an optoelectronically active diode part is formed in a semiconductor substrate by zones forming depletion layers. The system is provided in a mesa that stands vertically on a semiconductor substrate and runs in a direction of extension thereof. A light waveguide is optically coupled to the diode part in such a way that light is coupled into the diode part via the mesa side wall.

公开(公告)号：DE10242877A1

公开(公告)日：2004-03-25

申请号：DE10242877

申请日：2002-09-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ROESNER WOLFGANG ,  RISCH LOTHAR ,  HOFMANN FRANZ ,  SPECHT MICHAEL ,  LEHMANN VOLKER

IPC: H01L21/02 ,  H01L21/334 ,  H01L21/8242 ,  H01L21/84 ,  H01L27/108 ,  H01L27/12 ,  H01L29/94

Abstract: Semiconductor substrate comprises a carrier substrate (1), a semiconductor component layer (3), an insulating layer (2) arranged between the carrier substrate and the semiconductor component layer, recesses (P) formed in a surface facing the insulating layer in the carrier substrate, a dielectric layer (D) formed on the surface of the recesses and carrier substrate, and an electrically conducting layer (E2) formed in the recesses to produce capacitor electrodes. A further electrically conducting layer is formed in the carrier substrate to form capacitor counter electrodes in the region of the recesses. An Independent claim is also included for a process for the production of a semiconductor substrate.

公开(公告)号：DE59804824D1

公开(公告)日：2002-08-22

申请号：DE59804824

申请日：1998-09-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHWARZL SIEGFRIED ,  RISCH LOTHAR

IPC: G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/22 ,  H01L43/08

Abstract: A memory cell configuration has word lines and bit lines running transversely with respect thereto. Memory elements with a magnetoresistive effect are respectively connected between one of the word lines and one of the bit lines. The memory elements are disposed in at least two layers one above the other.

公开(公告)号：DE19933564C1

公开(公告)日：2001-01-25

申请号：DE19933564

申请日：1999-07-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHULZ THOMAS ,  ROESNER WOLFGANG ,  FRANOSCH MARTIN ,  SCHAEFER HERBERT ,  RISCH LOTHAR ,  AEUGLE THOMAS

IPC: H01L21/335 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/76 ,  H01L51/00 ,  H01L51/05 ,  H01L51/30 ,  H01L29/78

Abstract: According to the invention, a double gate MOSFET semiconductor layer structure is formed on a substrate (1). This structure is comprised of a first and of a second gate electrode (10A, 10B) between which a semiconductor channel layer zone (4A) is embedded, and of a source region (2A) and a drain region (2B) which are arranged on opposite faces of the semiconductor channel layer zone (4A). At least one additional semiconductor channel layer zone (6A) is provided on one of the gate electrodes (10B). The faces of the at least one additional semiconductor channel layer zone are also contacted by the source region (2A) and drain region (2B).