Abstract:
PROBLEM TO BE SOLVED: To provide a MOS transistor, where its CMOS-gate transit time is shortened as a short-channel type MOS transistor and its rising current is made rapid. SOLUTION: The manufacturing method of a MOS transistor comprises a step for providing in a semiconductor substrate a well having a dopant of a first conductive type, a step for providing an epitaxial layer on the surface of the doped well, a step for implanting into the epitaxial layer a dopant having a concentration lower than 1017/cm3, a step for providing in the epitaxial layer source/drain regions, having dopants of a second opposite conduction type to the first conduction type and a channel region, and a step for making the depths of the source/drain regions which is not larger than the thickness of the epitaxial layer.
Abstract:
According to the invention, the base resistance may be reduced and thus a low-resistance base electrode of a bipolar transistor produced, whereby a polysilicon layer is used as base electrode (2) in which impurity atoms, in particular C atoms are applied, which provide a high density of lattice holes in the polysilicon layer.
Abstract:
The invention concerns a semiconductor structure comprising a substrate (10), an insulating layer (14) arranged on one surface of the substrate (10), a layer (18) for components arranged on one surface (16) of the insulating layer (14) opposite the substrate (10), a semiconductor component (30a, 30b) arranged in the layer (18) for components and zone designed for capacitively uncoupling said semiconductor component (30a, 30b) relative to the substrate (10), said zone being formed by a space charge zone (96) formed in a region of the substrate (10) adjacent to the insulating layer (14).
Abstract:
The invention relates to a bipolar transistor (20) and to a method for producing the same. In order to obtain an as low a transition resistance as possible between the feed line (51) and the base (42), an intermediate layer (70) is provided between the first (30) and the second (40) layer, said intermediate layer (70) being selectively etchable to the second layer (40). At least in the zone of the undercut (43) between the feed line (51) and the base (42) a base connection zone (45) is provided that can be adjusted independent of other production conditions. The inventive transistor is further characterized in that the intermediate layer (70) is removed in the contact zone (46) with the base (42).
Abstract:
According to the invention, a double gate MOSFET semiconductor layer structure is formed on a substrate (1). This structure is comprised of a first and of a second gate electrode (10A, 10B) between which a semiconductor channel layer zone (4A) is embedded, and of a source region (2A) and a drain region (2B) which are arranged on opposite faces of the semiconductor channel layer zone (4A). At least one additional semiconductor channel layer zone (6A) is provided on one of the gate electrodes (10B). The faces of the at least one additional semiconductor channel layer zone are also contacted by the source region (2A) and drain region (2B).
Abstract:
Es werden ein Verfahren und ein System zum Bereitstellen eines Fusing nach der Kapselung von Halbleiterbauelementen bereitgestellt. Bei einer Ausführungsform wird ein Halbleiterbauelement bereitgestellt, das Folgendes umfasst: ein Substrat (202), das einen Fusebereich (206) aufweist, mindestens eine Fuse (208), die in dem Fusebereich (206) angeordnet ist, und mindestens eine Schicht (210), die über dem Substrat (202) angeordnet ist, wobei die mindestens eine Schicht (210) mindestens eine die mindestens eine Fuse (208) exponierende Öffnung (212) aufweist.
Abstract:
The method involves producing highly doped connection zones (10a-10c) in a semiconductor substrate (1) and a semiconductor layer in component areas (A, C), respectively. Another semiconductor layer is produced on the former layer that is produced on the substrate. Doped substances are implanted in the areas for forming a cathode zone of a varactor, which extends in a vertical direction until to the connection zones, and for forming a collector zone of a high frequency transistor, which extends in the vertical direction until to one of the zones, respectively.
Abstract:
Bipolar transistor comprises an emitter region (3) electrically contacted via an emitter electrode (1), a base region (4) electrically contacted via a base electrode (2), and a collector region (5) electrically contacted via a collector electrode. At least one of the electrodes contains silicon-germanium.