METHOD FOR PRODUCING TRENCH CAPACITORS
    1.
    发明申请
    METHOD FOR PRODUCING TRENCH CAPACITORS 审中-公开
    用于生产抓斗电容器

    公开(公告)号:WO0239501A3

    公开(公告)日:2003-03-13

    申请号:PCT/EP0112733

    申请日:2001-11-02

    CPC classification number: H01L27/1087

    Abstract: The invention relates to a method for producing trench capacitors having trenches (3-9) with mesopores (3-12). These trench capacitors are suited both for discrete capacitors and for integrated semiconductor memories. The mesopores significantly increase the surface for electrodes for the trench capacitors and thereby the capacitance of the trench capacitors. According to the invention, the mesopores, which are small channels similar to those made by woodworms and which have diameters ranging from 2 to 50 nm, are electrochemically produced. This method enables the production of capacitances with a high capacitance-to-volume ratio. The invention is additionally advantageous in that the growth of the mesopores stops once the mesopores reach a minimal distance from another mesopore or from adjacent trenches (self-passivation). As a result, the formation of short circuits between two adjacent mesopores can be prevented in a self-regulated manner. The invention also relates to a semiconductor component comprising at least one trench capacitor on the front side of a semiconductor substrate, which can be produced using the inventive method.

    Abstract translation: 提供了一种用于生产电容器的描述严重具有沟槽(3-9)与孔(3-12)。 这种严重的电容器适于分立电容器作为用于集成半导体存储器。 中孔增加的电极,用于电容器坟墓表面积,因此显著坟墓电容器的容量。 中孔是具有在根据本发明的通过电化学方法产生2至50nm范围内的直径小holzwurm孔状的通道。 该方法允许容量的产生具有大容量 - 体积比。 进一步的优点是,中孔的生长最新然后进入静止状态时的孔到达另一中孔或相邻的沟槽(个体钝化)的最小距离。 以这种方式,甚至调节“短裤”形成的两个相邻孔之间被避免。 此外,半导体器件描述了一种具有在其上可与本发明方法制造的半导体衬底的前侧的至少一个严重电容器。

    BIPOLAR TRANSISTOR
    2.
    发明申请
    BIPOLAR TRANSISTOR 审中-公开
    双极型晶体管

    公开(公告)号:WO0159845A2

    公开(公告)日:2001-08-16

    申请号:PCT/EP0101324

    申请日:2001-02-07

    CPC classification number: H01L29/66287 H01L29/7322

    Abstract: The invention relates to a bipolar transistor (20) and to a method for producing the same. In order to obtain an as low a transition resistance as possible between the feed line (51) and the base (42), an intermediate layer (70) is provided between the first (30) and the second (40) layer, said intermediate layer (70) being selectively etchable to the second layer (40). At least in the zone of the undercut (43) between the feed line (51) and the base (42) a base connection zone (45) is provided that can be adjusted independent of other production conditions. The inventive transistor is further characterized in that the intermediate layer (70) is removed in the contact zone (46) with the base (42).

    Abstract translation: 公开了一种双极型晶体管(20),以及用于其生产的方法。 所述双极晶体管(20)具有在其中设置的收集器(31)的第一,在基板(10)位于层(30),位于一个所述第一层(30)上的第二层(40)(碱切口 41)具有基部(42),至少一个另外的第三层(50)(第二层40上)设置并且其具有用于所述基部(42),其中,所述进料管线的进料管线(51)(51 )(在过渡区域52),以直接接触的所述基部(42),并且其中所述第三层(50)具有一个具有发射极的发射极的切口(53),和至少一个底切(43),其在所述第二层 (40)下面的所述第一(30)和第三之间的基底切口(41)(50)层设置,其特征在于,所述基部(42)至少部分地在所述底切(43)。 为了获得所述供应管线(51)和底座(42)之间的最低可能的过渡电阻,根据它提供的是,第一(30)之间的本发明和第二(40)层,中间层(70)设置,所述中间层(70)选择性地 形成以蚀刻第二层(40),至少在该底切之间(43)供应线(51)和基座(42)的基极端子区域(45)被提供,其可被调节的独立于其他制造条件的区域中,并且该中间层 (70)位于所述接触区(46)与所述基部(42)。

    Verfahren zum Entwickeln eines Photolacks

    公开(公告)号:DE102006030359B4

    公开(公告)日:2011-07-07

    申请号:DE102006030359

    申请日:2006-06-30

    Abstract: Verfahren zum Entwickeln eines Photolacks (13), mit folgenden Schritten: Anwenden (S9) eines ersten Entwicklers auf den Photolack (13), um nicht-vernetzte Bereiche (25) des Photolacks (13) zu entfernen; Anwenden (S11) eines zweiten Entwicklers auf den Photolack (13), um verbleibende nicht-vernetzte Bereiche (25) des Photolacks (13) zu entfernen, wobei sich der erste Entwickler und der zweite Entwickler in ihrer Zusammensetzung unterscheiden; und Beschießen oder In-Kontakt-Bringen des Photolacks (13) mit einem Sauerstoffplasma nach dem Schritt (S11) des Anwendens des zweiten Entwicklers.

    6.
    发明专利
    未知

    公开(公告)号:DE102008034159A1

    公开(公告)日:2009-02-05

    申请号:DE102008034159

    申请日:2008-07-22

    Abstract: It is proposed a method of manufacturing an electronic system wherein a first substrate comprising first connection elements on a first surface of the first substrate is provided; a second substrate comprising second connection elements on a first surface of the second substrate is provided; a polymer layer is applied to at least one of the two first surfaces; the first connection elements are attached to the second connection elements; and the polymer layer is caused to swell during or after the attachment.

    9.
    发明专利
    未知

    公开(公告)号:DE10063991B4

    公开(公告)日:2005-06-02

    申请号:DE10063991

    申请日:2000-12-21

    Abstract: A method for the manufacture of micro-mechanical components from a stack of layers having at least a substrate, a sacrificial layer and a layer which is to be undercut includes forming at least one etch hole in the layer, which is to be undercut, and providing at least one passivation layer for controlling a selective depositing of a cover material which closes each of the etch holes after a step of etching the sacrificial layer. The passivation layer makes it possible that the undercut layer elements do not become excessively thick or grow together with the substrate due to the deposition of the cover material.

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