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    SEMICONDUCTOR CIRCUIT ARRANGEMENT AND A METHOD FOR PRODUCING SAME
    1.
    发明申请
    SEMICONDUCTOR CIRCUIT ARRANGEMENT AND A METHOD FOR PRODUCING SAME 审中-公开
    半导体电路装置及其制造方法

    公开(公告)号：WO0141187A3

    公开(公告)日：2001-12-06

    申请号：PCT/EP0012051

    申请日：2000-11-30

    Applicant: INFINEON TECHNOLOGIES AG ,  HERZUM CHRISTIAN ,  MUELLER KARL HEINZ ,  KRUMBEIN ULRICH

    Inventor： HERZUM CHRISTIAN ,  MUELLER KARL-HEINZ ,  KRUMBEIN ULRICH

    IPC: H01L21/336 ,  H01L27/06 ,  H01L29/10 ,  H01L29/78 ,  H01L27/07

    CPC classification number: H01L29/66484 ,  H01L27/0629 ,  H01L29/1079 ,  H01L29/7831

    Abstract: The invention relates to a semiconductor circuit arrangement having a circuit element that is embodied in a semiconductor substrate (1) of a first conductivity type in an integrated manner and is provided with at least one gate electrode (G1, G2) and a first (D) and a second electrode (S). The first electrode connection (D) is configured by means of a connection tub that is embedded in the semiconductor substrate and pertains to a second conductivity type which is opposite the first conductivity type and a lower area of the connection tub, whereby said area is located in the connection tub, pertains to the second conductivity type and is higher doped in relation to the connection tub. The invention is characterised in that the lower area of the connection tub is embodied in the main surface of the semiconductor substrate, is allocated to the first electrode connection (D), pertains to the second conductivity type and ends in front of the tub area of the first conductivity type of the at least one gate electrode.

    Abstract translation: 本发明涉及一种具有半导体电路布置的在具有至少一个控制端的第一导电类型的集成电路形成的电路构件（G1，G2）和第一（D）和第二电极端子（S），的半导体衬底（1），其中，所述第一电极端子（D） 由一个内部嵌入在半导体基板连接的第二孔，所述第一导电类型的第二导电类型相反相对并位于第二导电类型的连接器托盘子阱区域内形成，但其更高度掺杂相比，连接桶。 本发明的特征在于，形成在半导体衬底的主表面，所述第一导电类型的端部的至少一个控制口的阱区之前与所述第二导电类型的子阱区相关联的所述第一电极端子（D）。

    Integrierter Transistor, insbesondere für Spannungen größer 40 Volt, und Herstellungsverfahren
    3.
    发明专利
    Integrierter Transistor, insbesondere für Spannungen größer 40 Volt, und Herstellungsverfahren 未知

    公开(公告)号：DE102004002181B4

    公开(公告)日：2011-08-18

    申请号：DE102004002181

    申请日：2004-01-15

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： ROESCHLAU KLAUS ,  MUELLER KARL-HEINZ

    IPC: H01L21/762 ,  H01L21/225 ,  H01L21/331 ,  H01L21/8222 ,  H01L21/8248 ,  H01L27/082 ,  H01L27/088 ,  H01L29/06 ,  H01L29/732 ,  H01L29/78

    Abstract: Integrierter Transistor (T1 bis T8), mit einem Halbleitersubstrat (10), mit einem im Halbleitersubstrat (10) enthaltenen vergrabenen hauptflächenfernen Anschlussbereich (14), der gemäß einem Grunddotiertyp dotiert ist, mit einem im Halbleitersubstrat (10) enthaltenen Driftbereich (50), der gemäß dem Grunddotiertyp mit einer geringeren Dotierstoffkonzentration als der hauptflächenferne Anschlussbereich (14) dotiert ist und der zwischen dem hauptflächenfernen Anschlussbereich (14) und der Hauptfläche (30) angeordnet ist, mit einem hauptflächennahen Anschlussbereich (58), der gemäß dem Grunddotiertyp dotiert ist, mit einem Umkehrdotierbereich (56), der gemäß einem anderen Dotiertyp als der Grunddotiertyp dotiert ist und der den Driftbereich (50) vom hauptflächennahen Anschlussbereich (58) trennt, mit einem elektrisch isolierenden Isoliergraben (48), der sich von der Hauptfläche (30) mindestens bis zum hauptflächenfernen Anschlussbereich (14) erstreckt und der der einzige Isoliergraben (48) ist zwischen dem Umkehrdotierbereich (56) und dem Hilfsgraben (46), und mit einem Hilfsgraben (46), der sich von der Hauptfläche (30) mindestens bis...

    4.
    发明专利
    未知

    公开(公告)号：DE50015714D1

    公开(公告)日：2009-09-24

    申请号：DE50015714

    申请日：2000-11-30

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： HERZUM CHRISTIAN ,  MUELLER KARL-HEINZ ,  KRUMBEIN ULRICH

    IPC: H01L21/28 ,  H01L29/78 ,  H01L21/336 ,  H01L27/02 ,  H01L27/06 ,  H01L27/07 ,  H01L29/10

    Abstract: The invention relates to a semiconductor circuit arrangement comprising a circuit element that is embodied in a semiconductor substrate (1) of a first conductivity type in an integrated manner and is provided with at least one gate electrode (G1, G2) and a first (D) and a second electrode connection (S). According to the invention, the at least one gate electrode is at least partially silicated on the side thereof facing away from the main surface of the semiconductor substrate.

    5.
    发明专利
    未知

    公开(公告)号：DE102006004209B3

    公开(公告)日：2007-09-06

    申请号：DE102006004209

    申请日：2006-01-30

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： MUELLER KARL-HEINZ ,  WINKLER BERNHARD

    IPC: B81C1/00 ,  B81B7/00

    Abstract: In a method for manufacturing a micromechanical device having a region for forming an integrated circuit, at first a first layer is produced on a deeper-lying part in the substrate. Subsequently, a membrane layer is produced on the first layer and at least one channel completely penetrating the membrane layer is introduced in the membrane layer. After that, a region of the first layer below the membrane layer is removed to form a cavity. Finally, the channel is sealed and a planar surface is formed.

    6.
    发明专利
    未知

    公开(公告)号：DE10326523A1

    公开(公告)日：2005-01-13

    申请号：DE10326523

    申请日：2003-06-12

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： MUELLER KARL-HEINZ ,  ROESCHLAU KLAUS

    IPC: H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L21/336

    Abstract: A field effect transistor (FET) and fabrication method are disclosed. The FET includes a drift region formed in a substrate. A trench adjoins the drift region and contains at least one control region and a connection region. An inversion channel region is isolated from the control region. A portion of the trench extends to the same depth as a second trench that insulates the FET from other components formed in the substrate. Insulating material is disposed between the trench below the control region and the control region. An insulating layer insulates the FET from the substrate. The trench and/or the connection region may extend into the insulating layer or may be isolated from the insulating layer via the drift region.

    7.
    发明专利
    未知

    公开(公告)号：DE102004002181A1

    公开(公告)日：2005-08-11

    申请号：DE102004002181

    申请日：2004-01-15

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： ROESCHLAU KLAUS ,  MUELLER KARL-HEINZ

    IPC: H01L21/225 ,  H01L21/331 ,  H01L21/762 ,  H01L29/06 ,  H01L29/732 ,  H01L29/78 ,  H01L27/088 ,  H01L21/8232

    Abstract: Integrated transistor and method for the production is disclosed. An explanation is given of, inter alia, a transistor having an electrically insulating isolating trench extending from a main area in the direction of a connection region remote from the main area. Moreover, the transistor contains an auxiliary trench extending from the main area as far as the connection region remote from the main area. The transistor requires a small chip area and has outstanding electrical properties.

    9.
    发明专利
    未知

    公开(公告)号：DE50110399D1

    公开(公告)日：2006-08-17

    申请号：DE50110399

    申请日：2001-05-04

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： MUELLER KARL-HEINZ ,  WOLF KONRAD

    IPC: H01L21/331

    Abstract: Production of a bipolar transistor comprises preparing a semiconductor substrate having a conducting region; applying a first insulating layer, a conducting layer and a second insulating layer to the substrate; applying a mask; anisotropically etching the insulating layers and isotropically etching the conducting layer to form an opening; forming a collector and a base in the opening by selective epitaxy; and producing an emitter. Preferred Features: The first insulating layer is made from silicon oxide. The second insulating layer is made from silicon nitride or silicon oxide. The conducting layer is made from polycrystalline silicon. The emitter is produced by a polycrystalline silicon deposition or by epitaxial deposition. The base has a layer of silicon-germanium.

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