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    SEMICONDUCTOR CIRCUIT ARRANGEMENT AND A METHOD FOR PRODUCING SAME
    1.
    发明申请
    SEMICONDUCTOR CIRCUIT ARRANGEMENT AND A METHOD FOR PRODUCING SAME 审中-公开
    半导体电路装置及其制造方法

    公开(公告)号：WO0141187A3

    公开(公告)日：2001-12-06

    申请号：PCT/EP0012051

    申请日：2000-11-30

    Applicant: INFINEON TECHNOLOGIES AG ,  HERZUM CHRISTIAN ,  MUELLER KARL HEINZ ,  KRUMBEIN ULRICH

    Inventor： HERZUM CHRISTIAN ,  MUELLER KARL-HEINZ ,  KRUMBEIN ULRICH

    IPC: H01L21/336 ,  H01L27/06 ,  H01L29/10 ,  H01L29/78 ,  H01L27/07

    CPC classification number: H01L29/66484 ,  H01L27/0629 ,  H01L29/1079 ,  H01L29/7831

    Abstract: The invention relates to a semiconductor circuit arrangement having a circuit element that is embodied in a semiconductor substrate (1) of a first conductivity type in an integrated manner and is provided with at least one gate electrode (G1, G2) and a first (D) and a second electrode (S). The first electrode connection (D) is configured by means of a connection tub that is embedded in the semiconductor substrate and pertains to a second conductivity type which is opposite the first conductivity type and a lower area of the connection tub, whereby said area is located in the connection tub, pertains to the second conductivity type and is higher doped in relation to the connection tub. The invention is characterised in that the lower area of the connection tub is embodied in the main surface of the semiconductor substrate, is allocated to the first electrode connection (D), pertains to the second conductivity type and ends in front of the tub area of the first conductivity type of the at least one gate electrode.

    Abstract translation: 本发明涉及一种具有半导体电路布置的在具有至少一个控制端的第一导电类型的集成电路形成的电路构件（G1，G2）和第一（D）和第二电极端子（S），的半导体衬底（1），其中，所述第一电极端子（D） 由一个内部嵌入在半导体基板连接的第二孔，所述第一导电类型的第二导电类型相反相对并位于第二导电类型的连接器托盘子阱区域内形成，但其更高度掺杂相比，连接桶。 本发明的特征在于，形成在半导体衬底的主表面，所述第一导电类型的端部的至少一个控制口的阱区之前与所述第二导电类型的子阱区相关联的所述第一电极端子（D）。

    METHOD FOR PRODUCING A STEPPED STRUCTURE ON A SUBSTRATE
    4.
    发明申请
    METHOD FOR PRODUCING A STEPPED STRUCTURE ON A SUBSTRATE 审中-公开
    在衬底上制造阶段 - 身体结构的方法

    公开(公告)号：WO03005411A3

    公开(公告)日：2003-09-18

    申请号：PCT/EP0207314

    申请日：2002-07-02

    Applicant: INFINEON TECHNOLOGIES AG ,  HERZUM CHRISTIAN

    Inventor： HERZUM CHRISTIAN

    IPC: H01L21/28 ,  H01L29/423 ,  H01L29/51

    CPC classification number: H01L21/28202 ,  H01L29/42368 ,  H01L29/513 ,  H01L29/518 ,  Y10S148/117 ,  Y10S438/942

    Abstract: The invention relates to a method for producing a stepped structure (132) on a substrate (100), with at least one first section with a first thickness and a second section with a second thickness, whereby firstly a sequence of layers, comprising a first oxide layer, a first nitride layer and a second oxide layer are applied to the substrate (100). A section of the second oxide layer and a section of the first nitride layer are then removed, in order to expose a section of the first oxide layer. A section of the first nitride layer is then removed to determine the first region of the stepped structure (132). The thickness of the first oxide layer, at least in the first fixed region, is altered, in order to fix the first thickness of said region. A further section of the first nitride region is then removed, in order to fix a second region of the stepped structure (132).

    Abstract translation: 在用于包括至少一个具有一第一厚度和具有第二厚度，首先第一氧化物层的层序列，第一氮化物层和第二部分的第一部分的衬底（100）上产生的阶梯结构（132）的方法 施加到衬底（100）的第二氧化物层。 随后，去除第二氧化物层的一部分和第一氮化物层的一部分以暴露第一氧化物层的一部分。 然后，去除第一氮化物层的一部分以限定台阶状结构（132）的第一区域。 随后，第一氧化物层的厚度至少在预定的第一范围内变化，以确定该区域的第一厚度。 随后，去除第一氮化物层的另一部分以限定台阶状结构（132）的第二区域。

    7.
    发明专利
    未知

    公开(公告)号：DE10131917A1

    公开(公告)日：2003-01-23

    申请号：DE10131917

    申请日：2001-07-02

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： HERZUM CHRISTIAN

    IPC: H01L21/28 ,  H01L29/423 ,  H01L29/51 ,  H01L21/336

    Abstract: The invention relates to a method for producing a stepped structure (132) on a substrate (100), with at least one first section with a first thickness and a second section with a second thickness, whereby firstly a sequence of layers, comprising a first oxide layer, a first nitride layer and a second oxide layer are applied to the substrate (100). A section of the second oxide layer and a section of the first nitride layer are then removed, in order to expose a section of the first oxide layer. A section of the first nitride layer is then removed to determine the first region of the stepped structure (132). The thickness of the first oxide layer, at least in the first fixed region, is altered, in order to fix the first thickness of said region. A further section of the first nitride region is then removed, in order to fix a second region of the stepped structure (132).

    8.
    发明专利
    未知

    公开(公告)号：DE19957533A1

    公开(公告)日：2001-06-07

    申请号：DE19957533

    申请日：1999-11-30

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： HERZUM CHRISTIAN ,  KRUMBEIN ULRICH ,  MUELLER KARLHEINZ

    IPC: H01L21/28 ,  H01L21/336 ,  H01L27/02 ,  H01L27/06 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/088

    Abstract: The invention relates to a semiconductor circuit arrangement comprising a circuit element that is embodied in a semiconductor substrate (1) of a first conductivity type in an integrated manner and is provided with at least one gate electrode (G1, G2) and a first (D) and a second electrode connection (S). According to the invention, the at least one gate electrode is at least partially silicated on the side thereof facing away from the main surface of the semiconductor substrate.

    9.
    发明专利
    未知

    公开(公告)号：DE50015714D1

    公开(公告)日：2009-09-24

    申请号：DE50015714

    申请日：2000-11-30

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： HERZUM CHRISTIAN ,  MUELLER KARL-HEINZ ,  KRUMBEIN ULRICH

    IPC: H01L21/28 ,  H01L29/78 ,  H01L21/336 ,  H01L27/02 ,  H01L27/06 ,  H01L27/07 ,  H01L29/10

    Abstract: The invention relates to a semiconductor circuit arrangement comprising a circuit element that is embodied in a semiconductor substrate (1) of a first conductivity type in an integrated manner and is provided with at least one gate electrode (G1, G2) and a first (D) and a second electrode connection (S). According to the invention, the at least one gate electrode is at least partially silicated on the side thereof facing away from the main surface of the semiconductor substrate.

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