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    Stacked semiconductor memory device
    1.
    发明专利
    Stacked semiconductor memory device 审中-公开
    堆叠半导体存储器件

    公开(公告)号：JP2006318634A

    公开(公告)日：2006-11-24

    申请号：JP2006132313

    申请日：2006-05-11

    Applicant: Infineon Technologies Ag ,  インフィネオン テクノロジーズ アクチエンゲゼルシャフト

    Inventor： MUFF SIMON ,  SCHROETER HOLGER ,  RAGHURAM SIVA ,  DJORDJEVIC SRDJAN

    IPC: G11C11/401

    CPC classification number: G11C5/02 ,  H01L25/105 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/0102 ,  H01L2924/01021 ,  H01L2924/01068 ,  H01L2924/3025 ,  H01L2224/05599

    Abstract: PROBLEM TO BE SOLVED: To make it possible to transmit a signal between a stacked semiconductor memory device and a controller with superior signal integrity even if the frequency of the bus or the load of the stacked semiconductor memory device is increased. SOLUTION: The stacked semiconductor memory device (100) includes memory device contacts (101) to externally connect the stacked semiconductor memory device to a printed circuit board. In a dual or quad stack configuration, the stacked semiconductor memory device includes a first package (110) which is stacked above a second package (120). The first and second packages are preferably designed as FBGA packages, each of them including package contacts (111, 121), respectively. By providing first and second flexible circuit structures (130, 140) to connect the package contacts of the first and second packages to the memory device contacts, a symmetrical stacked package configuration is obtained. COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：即使总线的频率或层叠的半导体存储器件的负载增加，也可以在堆叠的半导体存储器件和具有优异的信号完整性的控制器之间传输信号。 堆叠式半导体存储器件（100）包括将叠层半导体存储器件外部连接到印刷电路板的存储器件触点（101）。 在双堆叠或四堆叠配置中，堆叠的半导体存储器件包括堆叠在第二封装（120）之上的第一封装（110）。 第一和第二封装优选地被设计为FBGA封装，其分别包括封装触点（111,121）。 通过提供第一和第二柔性电路结构（130,140）来将第一和第二封装的封装触点连接到存储器件触点，获得对称的堆叠封装结构。 版权所有（C）2007，JPO＆INPIT

    DISPOSITIF DE MEMOIRE A SEMI-CONDUCTEURS EMPILE
    3.
    发明专利
    DISPOSITIF DE MEMOIRE A SEMI-CONDUCTEURS EMPILE 未知

    公开(公告)号：FR2891949A1

    公开(公告)日：2007-04-13

    申请号：FR0603843

    申请日：2006-04-28

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： MUFF SIMON ,  SCHROETER HOLGER ,  RAGHURAM SIVA ,  DJORDJEVIC SRDJAN

    IPC: H01L25/10 ,  G11C5/02

    Abstract: Un dispositif de mémoire à semi-conducteurs empilé (100) comprenant des contacts de dispositif de mémoire (101) pour connecter en externe le dispositif de mémoire à semi-conducteurs empilé à une carte à circuits imprimés. Dans une configuration d'empilage à deux étages ou à quatre étages, le dispositif de mémoire à semi-conducteurs empilé comprend un premier boîtier (110) qui est empilé au-dessus d'un deuxième boîtier (120). Les premier et deuxième boîtiers sont, de préférence, conçus sous la forme de boîtiers FBGA, et comprennent chacun des contacts de boîtier (111, 121). Le fait de prévoir une première et une deuxième structures de circuits flexibles (130, 140) pour connecter les contacts de boîtier (111, 121) des premier et deuxième boîtiers (110, 120) aux contacts de dispositif de mémoire (101) permet d'obtenir une configuration d'empilage de boîtiers symétrique.

    4.
    发明专利
    未知

    公开(公告)号：DE102005032061A1

    公开(公告)日：2007-01-11

    申请号：DE102005032061

    申请日：2005-07-08

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： RAGHURAM SIVA ,  MUFF SIMON

    IPC: G11C5/06 ,  G11C5/02

    Abstract: A memory extension memory module, a memory module system, and a memory module is disclosed. The memory module including at least one memory device and a connector for connecting the memory module to a computer system, wherein the memory module additionally includes a surface-mounted connector for connecting a memory extension memory module to the memory module. Furthermore, a method for manufacturing a memory module is disclosed. The memory module including at least one memory device and at least one connector for connecting a memory extension memory module to the memory module, wherein the at least one memory device and the at least one connector are connected to the memory module in a single manufacturing process.

    9.
    发明专利
    未知

    公开(公告)号：DE102006009561A1

    公开(公告)日：2006-09-14

    申请号：DE102006009561

    申请日：2006-02-28

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： RAGHURAM SIVA

    IPC: H01L25/18 ,  H01L23/31 ,  H01L23/498

    Abstract: A chip stack employing BGA or FBGA integrated circuit chip packages is provided. Two chip packages have bottom surfaces attached with sets of electrical contacts, which are oriented towards each other and are electrically connected to conductive patterns formed within the same flex substrate. One set contacts a conductive pattern on a top surface, the other set contacts a pattern on a bottom surface of the flex substrate within a same end portion. The other end portion has a conductive pattern, and is connected to a third set of electrical contacts. The flex substrate is wrapped around an edge of the chip package to connect the third set with the other two sets. Thereby, four chip packages are provided with this design, the layout of conductive traces formed within at least one of the flex substrates is meandered to compensate for length differences with respect to the other flex substrate.

    10.
    发明专利
    未知

    公开(公告)号：DE102005006831A1

    公开(公告)日：2006-08-17

    申请号：DE102005006831

    申请日：2005-02-15

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： DJORDJEVIC SRDJAN ,  RAGHURAM SIVA

    IPC: G11C11/4093 ,  G11C7/10

    Abstract: A semiconductor memory module has a module board on both sides of which semiconductor memory components are arranged and on an upper face of which a control component is arranged. The control component is connected to the semiconductor memory components via a module bus and bus spurs. The bus is a command address bus using fly-by topology. A semiconductor memory component is connected to the control component via a bus spur that is connected from a junction point to the two symmetrically arranged semiconductor memory components. An additional resistor between line sections of the bus spur reduces fluctuations of address signal levels on the CA bus and thus improves the signal integrity.

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