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公开(公告)号：DE102005026899A1
公开(公告)日：2006-12-14
申请号：DE102005026899
申请日：2005-06-10
Applicant: INFINEON TECHNOLOGIES AG
Inventor： STRAEUSNIGG DIETMAR , RAINER BERND , WIESBAUER ANDREAS , GAGGL RICHARD , CLARA MARTIN , HERNANDEZ LUIS
Abstract: A compensation circuit for a digital/analogue converter, which is clocked by a clock signal comprising a jitter and converts a digital input data signal into an analogue output data signal comprising a jitter error due to said jitter, comprises a measurement circuit for measuring the jitter and a modelling circuit for generating a digital modelled jitter error signal which simulates the jitter error dependent on the measured jitter and the digital input data signal, wherein the digital modelled jitter error signal is subtracted from the digital input data signal.
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公开(公告)号：DE102005026899B4
公开(公告)日：2007-02-22
申请号：DE102005026899
申请日：2005-06-10
Applicant: INFINEON TECHNOLOGIES AG
Inventor： STRAEUSNIGG DIETMAR , RAINER BERND , WIESBAUER ANDREAS , GAGGL RICHARD , CLARA MARTIN , HERNANDEZ LUIS
Abstract: A compensation circuit for a digital/analogue converter, which is clocked by a clock signal comprising a jitter and converts a digital input data signal into an analogue output data signal comprising a jitter error due to said jitter, comprises a measurement circuit for measuring the jitter and a modelling circuit for generating a digital modelled jitter error signal which simulates the jitter error dependent on the measured jitter and the digital input data signal, wherein the digital modelled jitter error signal is subtracted from the digital input data signal.
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