公开(公告)号：DE50112519D1

公开(公告)日：2007-07-05

申请号：DE50112519

申请日：2001-02-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FLECK ROD ,  IENNE PAOLO ,  OBERLAENDER KLAUS ,  RANDHAWA SABEEN ,  GAZIELLO LAURENT ,  MARTELLONI YANNICK ,  PAUL STEFFEN ,  SCHOEBER VOLKER

IPC: G01R31/28 ,  G11C29/00 ,  G11C29/04 ,  G11C29/24

Abstract: The testable read-only memory for data memory redundant logic has read-only memory units for storage of determined fault addresses of faulty data memory units. The serviceability of each read-only memory unit can be checked by application of input test data and by comparison of read output test data with expected nominal output test data.

公开(公告)号：DE60010511T2

公开(公告)日：2005-04-14

申请号：DE60010511

申请日：2000-12-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： OBERLAENDER KLAUS ,  RANDHAWA SABEEN ,  MARTELLONI YANNICK ,  HENFTLING MANFRED ,  ZEMACH RAMI ,  PELEG ZOHAR ,  WIEDHOLZ CHRISTIAN ,  BAROR GIGY ,  SHOHAM DORON ,  TRAININ ODED ,  MARGALIT NIV

IPC: G06F12/02

Abstract: An interface circuit for coupling a data handling unit with a memory unit having control inputs, an address signal input, a data signal input, and a data signal output is described. The interface circuit comprises an address buffer having an input and an output, said input receiving an address signal from said data handling unit, a first multiplexer which couples said memory unit with either said output of said address buffer or with said address signal, a data buffer having an input and an output, said input receiving a data signal from said data handling unit and said output being coupled with said memory data input, a second multiplexer for selecting either said memory data signal output or said data buffer output, and a comparator for comparing said address signal with the signal from said address buffer output, generating a control signal which controls said second multiplexer.

公开(公告)号：DE60010511D1

公开(公告)日：2004-06-09

申请号：DE60010511

申请日：2000-12-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： OBERLAENDER KLAUS ,  RANDHAWA SABEEN ,  MARTELLONI YANNICK ,  HENFTLING MANFRED ,  ZEMACH RAMI ,  PELEG ZOHAR ,  WIEDHOLZ CHRISTIAN ,  BAROR GIGY ,  SHOHAM DORON ,  TRAININ ODED ,  MARGALIT NIV

IPC: G06F12/02

Abstract: An interface circuit for coupling a data handling unit with a memory unit having control inputs, an address signal input, a data signal input, and a data signal output is described. The interface circuit comprises an address buffer having an input and an output, said input receiving an address signal from said data handling unit, a first multiplexer which couples said memory unit with either said output of said address buffer or with said address signal, a data buffer having an input and an output, said input receiving a data signal from said data handling unit and said output being coupled with said memory data input, a second multiplexer for selecting either said memory data signal output or said data buffer output, and a comparator for comparing said address signal with the signal from said address buffer output, generating a control signal which controls said second multiplexer.