公开(公告)号：JP2005322914A

公开(公告)日：2005-11-17

申请号：JP2005133874

申请日：2005-05-02

Applicant: Infineon Technologies Ag ,  インフィネオン テクノロジーズ アクチエンゲゼルシャフト

Inventor： CAPTEYN CHRISTIAN ,  REGUL JOERN

IPC: H01L27/108 ,  H01L21/8234 ,  H01L21/8242

CPC classification number: H01L27/10861 ,  H01L27/10829 ,  H01L27/10867

Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing a trench capacitor, a method of manufacturing a memory cell, the trench capacitor and the memory cell.
SOLUTION: The method of manufacturing a storage capacitor (23) comprising a first capacitor electrode (6), a first dielectric layer (7), a second capacitor electrode (8), a second dielectric layer (9) and a third capacitor electrode (10). The first capacitor electrode (6) and the third capacitor electrode are connected to each other. In this method, the first capacitor electrode (6) and the third capacitor electrode (10) are formed by conformal deposition method; whereas, the first dielectric layer (7), the second capacitor electrode (8) and the second dielectric layer (9) are formed by non-conformal method. Accordingly, the trench capacitor, in which storage capacitance is increased, can be made.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种制造沟槽电容器的方法，制造存储单元的方法，沟槽电容器和存储单元。 解决方案：制造包括第一电容器电极（6），第一介电层（7），第二电容器电极（8），第二介电层（9）和第三电容器（9）的存储电容器（23）的方法 电容电极（10）。 第一电容器电极（6）和第三电容器电极彼此连接。 在该方法中，第一电容器电极（6）和第三电容器电极（10）通过保形沉积法形成; 而第一电介质层（7），第二电容器电极（8）和第二电介质层（9）通过非共形方法形成。 因此，可以制造其中增加存储电容的沟槽电容器。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：DE102004022602A1

公开(公告)日：2005-12-15

申请号：DE102004022602

申请日：2004-05-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KAPTEYN CHRISTIAN ,  REGUL JOERN

IPC: H01L27/108 ,  H01L21/8234 ,  H01L21/8242

Abstract: A memory cell having a trench capacitor, a trench capacitor, and a method is disclosed. In one embodiment, the method for fabricating a trench capacitor with a first capacitor electrode, a first capacitor dielectric, a second capacitor electrode, a second capacitor dielectric and third capacitor electrode, includes connecting the first and third capacitor electrodes. The first and third capacitor electrodes are formed by conformal deposition methods, whereas the first capacitor dielectric, the second capacitor electrode and the second capacitor dielectric are formed by nonconformal deposition methods.

公开(公告)号：DE102005024952A1

公开(公告)日：2007-01-18

申请号：DE102005024952

申请日：2005-05-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MUEMMLER KLAUS ,  BAARS PETER ,  ARNDT CHRISTIAN ,  REGUL JOERN

IPC: H01L21/8242

Abstract: The method involves producing a conductive layer (8) on a dielectric layer (11) with opening areas above a conducting path (3) and above capacitor electrodes (7). The dielectric layer is selectively etched to the conductive layer for forming trenches that are partially dissected in a surface of the conducting path and ends in the conductive layer above the capacitor electrodes. The trenches are filled with conductive material. An independent claim is also included for a semiconductor device e.g. semiconductor memory device.

公开(公告)号：DE102006018235B3

公开(公告)日：2007-10-11

申请号：DE102006018235

申请日：2006-04-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： REGUL JOERN ,  MUELLER TORSTEN ,  KAPTEYN CHRISTIAN ,  BAARS PETER ,  MUEMMLER KLAUS

IPC: H01L27/115 ,  G11C5/06 ,  H01L21/8247

Abstract: The component has a substrate at a main side, where lower bit lines (LBL1- LBL6) are formed in the substrate and are arranged parallel to each other at a distance. Word lines (WL1- WL10) are arranged over the lower bit lines parallel to each other at a distance and transverse to the lower bit lines. A gate-dielectric arranged between the word lines and cell bodies includes a memory layer as a memory medium. Lower source and/or drain regions are formed at lower lines of the bodies adjacent to the lower bit lines, and upper source and/or drain regions are formed in upper lines of the bodies. An independent claim is also included for a method for manufacturing semiconductor memory components.

公开(公告)号：DE102004029516B3

公开(公告)日：2005-12-29

申请号：DE102004029516

申请日：2004-06-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TEMMLER DIETMAR ,  REGUL JOERN

IPC: B81C1/00 ,  H01L21/265 ,  H01L21/31 ,  H01L21/3213 ,  H01L21/8242

Abstract: The present invention provides a method for fabricating a shadow mask in a trench of a microelectronic or micromechanical structure, comprising the steps of: providing a trench in the microelectronic or micromechanical structure; providing a partial filling in the trench; providing a first liner mask layer on the partial filling; providing a sacrificial filling on the liner mask layer to completely fill the trench; shallow etching back of the sacrificial filling into the trench; forming a first mask on the top side of the sacrificial filling in the trench; removing a subregion of the sacrificial filling in the trench using the first mask; and optionally removing a subregion of the first liner mask layer below it on the partial filling, the remaining subregion of the sacrificial filling in the trench serving as a second mask.