公开(公告)号：DE102005057255B4

公开(公告)日：2007-09-20

申请号：DE102005057255

申请日：2005-12-01

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BERNHARDT HENRY ,  HECHT THOMAS ,  STADTMUELLER MICHAEL ,  KIM YEONG KWAN ,  KAPTEYN CHRISTIAN ,  SCHROEDER UWE ,  SPITZER ANDREAS

IPC: H01L27/108 ,  H01L21/8242

Abstract: The capacitor has a first electrode layer (103), a second electrode layer (104,105) and a dielectric intermediate layer (110) between the electrode layers. The dielectric layer contains a high k dielectric and at least one component containing silicon. Independent claims also cover a method of manufacture.

公开(公告)号：DE102005056262A1

公开(公告)日：2007-05-31

申请号：DE102005056262

申请日：2005-11-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KREUPL FRANZ ,  LIEBAU MAIK ,  DUESBERG GEORG STEFAN ,  KAPTEYN CHRISTIAN

IPC: H01L21/822 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/532 ,  H01L27/08

Abstract: Producing a layer arrangement comprises forming a layer of essentially carbon followed by a protective layer and then an electrically isolating layer so that the carbon layer is protected from damage during the formation of the electrically isolating layer. Preferably the protective layer is a carbide. Independent claims are also included for the following: (A) producing an electrical component; (B) a layer arrangement as above; and (C) an electrical component as above.

公开(公告)号：DE102006018235B3

公开(公告)日：2007-10-11

申请号：DE102006018235

申请日：2006-04-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： REGUL JOERN ,  MUELLER TORSTEN ,  KAPTEYN CHRISTIAN ,  BAARS PETER ,  MUEMMLER KLAUS

IPC: H01L27/115 ,  G11C5/06 ,  H01L21/8247

Abstract: The component has a substrate at a main side, where lower bit lines (LBL1- LBL6) are formed in the substrate and are arranged parallel to each other at a distance. Word lines (WL1- WL10) are arranged over the lower bit lines parallel to each other at a distance and transverse to the lower bit lines. A gate-dielectric arranged between the word lines and cell bodies includes a memory layer as a memory medium. Lower source and/or drain regions are formed at lower lines of the bodies adjacent to the lower bit lines, and upper source and/or drain regions are formed in upper lines of the bodies. An independent claim is also included for a method for manufacturing semiconductor memory components.

公开(公告)号：DE102005051819B3

公开(公告)日：2007-06-14

申请号：DE102005051819

申请日：2005-10-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： JAKISCH STEFAN ,  KAPTEYN CHRISTIAN ,  HECHT THOMAS

IPC: H01L21/314 ,  H01L21/311 ,  H01L21/336 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/08

Abstract: In a method for producing a semiconductor structure a substrate is provided, a dielectric layer comprising at least one metal oxide is formed on the substrate, and a nitrided layer is formed from the dielectric layer. The nitrided layer comprises either at least one metal nitride corresponding to the metal oxide or a metal oxynitride. The nitrided layer is removed selectively with respect to the dielectric layer in a predetermined etching medium.

公开(公告)号：DE102006016530A1

公开(公告)日：2007-10-11

申请号：DE102006016530

申请日：2006-04-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KAPTEYN CHRISTIAN ,  KUDELKA STEPHAN

IPC: H01L27/108 ,  H01L21/8242

Abstract: A storage capacitor has two memory electrodes (102, 107), and a memory dielectric (103) arranged between the memory electrodes. An intermediate layer (109) made of pure carbon is 1-50 nm thick. An electrode layer (108) is made of phosphorus doped polysilicon, and another electrode layer (110) is made of arsenic doped polysilicon. The dielectric includes a thin layer or a stack of thin layers. The electrode layer (108) is provided for completely covering the dielectric. An independent claim is also included for the production of a storage capacitor.

公开(公告)号：DE102005057255A1

公开(公告)日：2007-06-14

申请号：DE102005057255

申请日：2005-12-01

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BERNHARDT HENRY ,  HECHT THOMAS ,  STADTMUELLER MICHAEL ,  KIM YEONG KWAN ,  KAPTEYN CHRISTIAN ,  SCHROEDER UWE ,  SPITZER ANDREAS

IPC: H01L27/108 ,  H01L21/8242

Abstract: The capacitor has a first electrode layer (103), a second electrode layer (104,105) and a dielectric intermediate layer (110) between the electrode layers. The dielectric layer contains a high k dielectric and at least one component containing silicon. Independent claims also cover a method of manufacture.

公开(公告)号：DE102004022602A1

公开(公告)日：2005-12-15

申请号：DE102004022602

申请日：2004-05-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KAPTEYN CHRISTIAN ,  REGUL JOERN

IPC: H01L27/108 ,  H01L21/8234 ,  H01L21/8242

Abstract: A memory cell having a trench capacitor, a trench capacitor, and a method is disclosed. In one embodiment, the method for fabricating a trench capacitor with a first capacitor electrode, a first capacitor dielectric, a second capacitor electrode, a second capacitor dielectric and third capacitor electrode, includes connecting the first and third capacitor electrodes. The first and third capacitor electrodes are formed by conformal deposition methods, whereas the first capacitor dielectric, the second capacitor electrode and the second capacitor dielectric are formed by nonconformal deposition methods.