公开(公告)号：DE10061243A1

公开(公告)日：2002-06-27

申请号：DE10061243

申请日：2000-12-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ROHLEDER MARKUS ,  DOBLER MANFRED

IPC: G11C7/10 ,  G11C29/50 ,  G11C29/00

Abstract: The data propagatiom time determination method has a signal sequence supplied to the semiconductor memory, for transfer of test data written into at least one memory cell to an output buffer via the databus, with subsequent transfer of the data in the output buffer to the memory output and comparison of the output data with the original test data. The process is repeated with the interval between transfer of the test data to the buffer and transfer to the memory output extended until no fault is indicated between the compared data. An Independent claim for a device for determining the propagation time of data along a databus in a semiconductor memory is also included.

公开(公告)号：DE102004052594B3

公开(公告)日：2006-05-04

申请号：DE102004052594

申请日：2004-10-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ROHLEDER MARKUS

IPC: G11C29/14

公开(公告)号：DE10057275C1

公开(公告)日：2002-06-06

申请号：DE10057275

申请日：2000-11-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： DOBLER MANFRED ,  ROHLEDER MARKUS

IPC: G11C11/406

Abstract: The refreshing device (1) has a control device (12) supplying a periodic sequence of control signals for initiating information refreshing of the memory cells, which is variable in dependence on the storage time of the information held in each memory cell. A test circuit (13) coupled to the control device provides the maximum storage time of the individual memory cells, for controlling the refresh control signal periodic sequence. An Independent claim for a method for controlling information refreshing for the memory cells of a dynamic random-access memory is also included.

公开(公告)号：DE10323413B4

公开(公告)日：2006-01-19

申请号：DE10323413

申请日：2003-05-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HERRMANN KONRAD ,  SCHELLINGER ANDREAS ,  MAYER PETER ,  ROHLEDER MARKUS

IPC: G01R31/3181 ,  G01R31/319 ,  G11C29/00 ,  G11C29/56

Abstract: Test method for testing high speed semiconductor memory (1), especially DDR-DRAM modules using a test device (4) and a memory control unit. A test signal bus (51') is used to link a test signal unit (41') with the test device. The test signal unit is provided by a memory control unit or a simplified memory control unit derived from a memory control unit and is integrated in the test socket (2'). Independent claims are also included for the following:- (a) a test arrangement for testing semiconductor memory circuits and; (b) a test socket for testing semiconductor memory in conjunction with a memory control unit.

公开(公告)号：DE10120764B4

公开(公告)日：2004-12-23

申请号：DE10120764

申请日：2001-04-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： STIEF REIDAR ,  ROHLEDER MARKUS

IPC: H03L7/081 ,  H03L7/093 ,  G06F1/12 ,  H04L7/033

Abstract: A circuit for synchronizing signals during an exchange of information between circuits, in particular between computer chips, of a system of circuits, is described. The configuration has a delay locked loop (DLL) circuit for synchronizing an internal clock between a respective circuit and an external clock of the circuit system according to the phase difference between the two clocks in a manner dependent on phase changes in the signals. A response sensitivity of the DLL circuit is defined by a filter, which enables a renewed synchronization only after the arrival of a plurality of phase change events. The filter provided for setting the response sensitivity of the DLL circuit is of a variable configuration.

公开(公告)号：DE10319516A1

公开(公告)日：2004-12-09

申请号：DE10319516

申请日：2003-04-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HERRMANN KONRAD ,  SCHELLINGER ANDREAS ,  MAYER PETER ,  ROHLEDER MARKUS

IPC: G11C29/56 ,  G11C29/00

Abstract: Test method for semiconductor memory modules, especially high speed DDR-DRAMS, that are operated in conjunction with a memory control unit. According to the method a number of suitable memory control units are selected as test memory control units (44) and are provided as part of a test device (3). The test data signals given out from the semiconductor memory modules under test are evaluated using the test memory control units. An independent claim is made for a test device for semiconductor memory modules.

公开(公告)号：DE10057202A1

公开(公告)日：2002-02-21

申请号：DE10057202

申请日：2000-11-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ANGENENDT GUIDO ,  ROHLEDER MARKUS

IPC: G11C29/48 ,  G11C29/00

Abstract: The arrangement has a test computer unit (19) that is connected to a circuit board connection connected to input/outputs of the memory component (2,3) on the board (1) and that reads control data from a memory element (15) and checks the functionality of the memory component from the data. The memory component is a graphic memory component. A second graphic memory component can be mounted on the board.

公开(公告)号：DE10323413A1

公开(公告)日：2004-12-23

申请号：DE10323413

申请日：2003-05-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HERRMANN KONRAD ,  SCHELLINGER ANDREAS ,  MAYER PETER ,  ROHLEDER MARKUS

IPC: G01R31/319 ,  G11C29/56 ,  G11C29/00 ,  G01R31/3181

Abstract: Test method for testing high speed semiconductor memory (1), especially DDR-DRAM modules using a test device (4) and a memory control unit. A test signal bus (51') is used to link a test signal unit (41') with the test device. The test signal unit is provided by a memory control unit or a simplified memory control unit derived from a memory control unit and is integrated in the test socket (2'). Independent claims are also included for the following:- (a) a test arrangement for testing semiconductor memory circuits and; (b) a test socket for testing semiconductor memory in conjunction with a memory control unit.

公开(公告)号：DE10232178B3

公开(公告)日：2004-02-26

申请号：DE10232178

申请日：2002-07-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ROHLEDER MARKUS ,  WELLER JOERG ,  MAYER PETER ,  GREWE MATTHIAS

IPC: G11C29/02 ,  G11C29/20 ,  G01R31/3187 ,  G11C29/00

Abstract: The checking device has a memory device (FF) with a number of memory elements (FF0-FF3) respectively storing the values of address signals supplied by the address generator (AGen) to the lines (B0-B3) of an address bus (A0-A3) of the IC, the stored values delivered to at least one terminal position (pd) of the IC via a controlled switch (T). An Independent claim for a checking method for an address generator forming part of a testing device within an IC is also included.

公开(公告)号：DE10120764A1

公开(公告)日：2002-11-07

申请号：DE10120764

申请日：2001-04-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： STIEF REIDAR ,  ROHLEDER MARKUS

IPC: H03L7/081 ,  H03L7/093 ,  G06F1/12 ,  H04L7/033

Abstract: A circuit for synchronizing signals during an exchange of information between circuits, in particular between computer chips, of a system of circuits, is described. The configuration has a delay locked loop (DLL) circuit for synchronizing an internal clock between a respective circuit and an external clock of the circuit system according to the phase difference between the two clocks in a manner dependent on phase changes in the signals. A response sensitivity of the DLL circuit is defined by a filter, which enables a renewed synchronization only after the arrival of a plurality of phase change events. The filter provided for setting the response sensitivity of the DLL circuit is of a variable configuration.