公开(公告)号：DE19815874C2

公开(公告)日：2002-06-13

申请号：DE19815874

申请日：1998-04-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： RUSCH ANDREAS ,  OTANI YOICHI ,  ROTHENHAEUSER STEFFEN ,  TRUEBY ALEXANDER ,  ZIMMERMANN ULRICH

IPC: H01L21/822 ,  H01L21/8246 ,  H01L27/04 ,  H01L27/10 ,  H01L27/112

Abstract: A method for fabricating a semiconductor memory device is described. An insulating layer is disposed on a semiconductor substrate. A matrix of semiconductor memory elements is disposed in the substrate. The semiconductor memory elements include a plurality of contact holes formed in the insulating layer. One contact hole is formed in the insulating layer for each of the semiconductor memory elements. A bit definition region is disposed in the semiconductor substrate underneath each of the contact holes. A contact plug is disposed in each of the contact holes and is in electrical contact with the bit definition region. The bit definition region is configured such that a contact resistance between the semiconductor substrate and the contact plug defines a bit to be stored in the semiconductor memory elements, An evaluation circuit is connected to and evaluates the contact resistance of the semiconductor memory elements.

公开(公告)号：DE10254473B4

公开(公告)日：2006-11-30

申请号：DE10254473

申请日：2002-11-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ROTHENHAEUSER STEFFEN ,  STAHRENBERG KNUT

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L27/06

公开(公告)号：DE10254473A1

公开(公告)日：2004-06-09

申请号：DE10254473

申请日：2002-11-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ROTHENHAEUSER STEFFEN ,  STAHRENBERG KNUT

IPC: H01L21/8238 ,  H01L21/8234 ,  H01L21/8249

Abstract: Production of an integrated semiconductor circuit comprises introducing a first active zone (1a, 1b) and a second active zone (1a', 1b') into a semiconductor substrate, applying a first dielectric layer (3) over the first active zone and second active zone, applying a second dielectric layer (4) on the first dielectric layer, removing the second dielectric layer over the second active zone, applying a third dielectric layer over the second active zone, producing a gate electrode (7') over the first active zone and the second active zone, and introducing a source and drain region into the two active zones. An Independent claim is also included for an alternative process for the production of an integrated semiconductor circuit.