1.
    发明专利
    未知

    公开(公告)号:DE59914356D1

    公开(公告)日:2007-07-12

    申请号:DE59914356

    申请日:1999-09-17

    Abstract: Doped region production involves thermally diffusing dopant from a semiconductor layer through an insulating interlayer (40, 70) and then making the interlayer (40, 70) electrically conductive. A doped region is produced by: (a) successively applying an insulating interlayer (40, 70) and a first conductivity type doped semiconductor layer onto a semiconductor substrate (15); (b) annealing the substrate so that dopant diffuses from the semiconductor layer through the interlayer (40, 70) into the substrate to form one or more first conductivity type doped regions (55, 80); and (c) altering the electrical conductivity of the interlayer (40, 70) to produce electrical contact between the doped region (55, 80) and the semiconductor layer. Preferred Features: The interlayer (40, 70) consists of silicon oxide and is made conductive by a voltage or current pulse.

    2.
    发明专利
    未知

    公开(公告)号:DE59813593D1

    公开(公告)日:2006-07-27

    申请号:DE59813593

    申请日:1998-03-06

    Abstract: A CMOS circuit production process includes formation of insulating sidewall spacers (19) on the p-channel MOST gate electrode (16) and then forming p-doped single crystal silicon structures (112), acting as diffusion sources for forming the source/drain regions (113) of the p-channel MOST, at the side of the gate electrode (16) by a selective epitaxy step which avoids silicon deposition on insulating material and n-doped silicon surfaces. Preferably, the n-doped source/drain regions (111) for the n-channel MOST are formed prior to the selective epitaxy step, which is carried out using a process gas containing H2, HCl, SiH2Cl2 and B2H6 at 700-900 degrees C at 1-700 Torr.

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