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    INTEGRATED MEMORY AND OPERATING METHOD THEREFOR
    1.
    发明专利
    INTEGRATED MEMORY AND OPERATING METHOD THEREFOR 失效

    公开(公告)号：JP2000348485A

    公开(公告)日：2000-12-15

    申请号：JP2000143734

    申请日：2000-05-16

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SCHLAGER TOBIAS ,  MANYOKI ZOLTAN ,  ESTERL ROBERT

    IPC: G11C14/00 ,  G11C11/22 ,  G11C11/409 ,  G11C11/41

    Abstract: PROBLEM TO BE SOLVED: To make generable a reference voltage in a comparatively short time by a method wherein a first switching element which is used to connect two bit lines and a selection transistor for two reference memory cells are turned on, only the selection transistor is turned off after a prescribed period, and the potential difference between the two bit lines is offset. SOLUTION: A first switching element S1 which short-circuits a first and second bit lines BL1 and the inverse of BL1, and a selection transistor for two reference memory cells RCs are turned on by a control unit C1. After a prescribed period has elaped, the first switching element S1 is continuously set to continuity, and the potential difference between the bit lines BL1 and the inverse of BL1 is offset. Consequently, the influence of the nonlinear memory capacitor of the reference memory cells RCs on a reference voltage is smaller than that, in a case where the selection transistor is set to continuity up to the perfect equilibrium of an electric charge between the bit lines BL1 and the inverse of BL1.

    4.
    发明专利
    未知

    公开(公告)号：FR2856509B1

    公开(公告)日：2007-01-26

    申请号：FR0406327

    申请日：2004-06-11

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： DIRSCHERL GERD ,  SEDLAK HOLGER ,  SCHLAGER TOBIAS

    IPC: G11C29/00 ,  G06K19/073 ,  G11C16/34

    Abstract: Test reading apparatus having a memory device having individual memory cells, a buffer device, which is connected to the memory device, and which stores data written to the memory cells in the memory device, an apparatus which has an input and an output, at least one test reference source which can be connected to the input of the apparatus by data stored in the buffer device, and a test apparatus, which is connected to the buffer device and to the output of the apparatus, and which is designed to compare a signal at the output of the apparatus with data stored in the buffer device.

    5.
    发明专利
    未知

    公开(公告)号：DE10327284B4

    公开(公告)日：2005-11-03

    申请号：DE10327284

    申请日：2003-06-17

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： DIRSCHERL GERD ,  SCHLAGER TOBIAS ,  SEDLAK HOLGER

    IPC: G11C16/34 ,  G11C29/00 ,  G01R19/165 ,  G01R31/3181 ,  G01R31/3193 ,  H05K13/08

    Abstract: Test reading apparatus having a memory device having individual memory cells, a buffer device, which is connected to the memory device, and which stores data written to the memory cells in the memory device, an apparatus which has an input and an output, at least one test reference source which can be connected to the input of the apparatus by data stored in the buffer device, and a test apparatus, which is connected to the buffer device and to the output of the apparatus, and which is designed to compare a signal at the output of the apparatus with data stored in the buffer device.

    6.
    发明专利
    未知

    公开(公告)号：DE19915081C2

    公开(公告)日：2001-10-18

    申请号：DE19915081

    申请日：1999-04-01

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SCHLAGER TOBIAS ,  HOENIGSCHMID HEINZ

    IPC: G11C11/22

    Abstract: An integrated memory in which the plate lines run parallel to the bit lines and are driven by the column decoder. The effect achieved by the fact that each plate line is connected to the memory cells of the associated bit line is that only those memory cells whose associated bit line is required for the respective memory access are affected by the pulsed signals of the plate line. Therefore, only the potential of that bit line which is currently required for a data transfer is influenced by pulsed signals on the associated plate lines.

    10.
    发明专利
    未知

    公开(公告)号：DE10327284A1

    公开(公告)日：2005-01-13

    申请号：DE10327284

    申请日：2003-06-17

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： DIRSCHERL GERD ,  SCHLAGER TOBIAS ,  SEDLAK HOLGER

    IPC: G11C16/34 ,  G11C29/00 ,  G01R19/165 ,  G01R31/3181 ,  G01R31/3193 ,  H05K13/08

    Abstract: Test reading apparatus having a memory device having individual memory cells, a buffer device, which is connected to the memory device, and which stores data written to the memory cells in the memory device, an apparatus which has an input and an output, at least one test reference source which can be connected to the input of the apparatus by data stored in the buffer device, and a test apparatus, which is connected to the buffer device and to the output of the apparatus, and which is designed to compare a signal at the output of the apparatus with data stored in the buffer device.

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