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    Charge capture semiconductor memory device
    1.
    发明专利
    Charge capture semiconductor memory device 审中-公开
    充电半导体存储器件

    公开(公告)号：JP2006086522A

    公开(公告)日：2006-03-30

    申请号：JP2005257159

    申请日：2005-09-05

    Applicant: Infineon Technologies Ag ,  インフィネオン テクノロジーズ アクチエンゲゼルシャフト

    Inventor： VERHOEVEN MARTIN

    IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC classification number: H01L27/115 ,  H01L27/11553 ,  H01L27/11568 ,  H01L29/7881 ,  H01L29/792 ,  H01L29/7926

    Abstract: PROBLEM TO BE SOLVED: To provide a charge capture semiconductor memory device whose size is further reduced.
    SOLUTION: A memory cell is preferably formed by a cylindrical recess (2), in a main surface of a semiconductor substrate (1) and is provided with a memory layer sequence (3) and a gate electrode (4) in a sidewall. An upper source/drain region (5) and a lower source/drain region (6) which are connected in a queue to a first bit line (8), and a second bit line (9) are provided. A word line (10) is arranged on the upper part of the first bit line (8), and the second bit line (9) and is connected to a row of the gate electrode (4). A transistor structure in the vertical direction facilitates further miniaturization of cells and enables making desired minimum effective channel length.
    COPYRIGHT: (C)2006,JPO&NCIPI

    Abstract translation: 解决的问题：提供尺寸进一步降低的电荷捕获半导体存储器件。 解决方案：存储单元优选地由半导体衬底（1）的主表面中的圆柱形凹部（2）形成，并且在其中设置有存储层序列（3）和栅电极（4） 侧壁。 提供了以队列方式连接到第一位线（8）和第二位线（9）的上部源极/漏极区域（5）和下部源极/漏极区域（6）。 字线（10）布置在第一位线（8）的上部，第二位线（9）连接到栅电极（4）的一行。 在垂直方向上的晶体管结构有利于细胞的进一步小型化，并且能够实现期望的最小有效通道长度。 版权所有（C）2006，JPO＆NCIPI

    METHOD FOR PRODUCTION OF CHARGE-TRAPPING MEMORY CELLS
    2.
    发明申请
    METHOD FOR PRODUCTION OF CHARGE-TRAPPING MEMORY CELLS 审中-公开
    电荷捕获存储单元的生产方法

    公开(公告)号：WO2006040165A3

    公开(公告)日：2006-06-08

    申请号：PCT/EP2005011039

    申请日：2005-10-13

    Applicant: INFINEON TECHNOLOGIES AG ,  VERHOEVEN MARTIN

    Inventor： VERHOEVEN MARTIN

    IPC: H01L29/792 ,  H01L21/336

    CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L29/66833

    Abstract: An oxide layer (2), a nitride layer (3), and a layer of amorphous silicon (4) are applied to a surface of a semiconductor substrate (1). A resist mask (5) is applied and implantations are performed to form doped regions (6) of source and drain and doped regions within the amorphous silicon layer. The resist mask and undoped parts of the amorphous silicon are removed to form a silicon mask (7). The silicon mask is applied to etch back the nitride layer (3). After a removal of the silicon mask (7), the nitride (3) is oxidized to form an oxide-nitride-oxide layer sequence which is laterally restricted to the area above the source/drain regions (6).

    Abstract translation: 将氧化物层（2），氮化物层（3）和非晶硅层（4）施加到半导体衬底（1）的表面。 施加抗蚀剂掩模（5）并进行注入以在非晶硅层内形成源极和漏极和掺杂区域的掺杂区域（6）。 去除抗蚀剂掩模和非晶硅的未掺杂部分以形成硅掩模（7）。 施加硅掩模以蚀刻氮化物层（3）。 在去除硅掩模（7）之后，氮化物（3）被氧化以形成横向限于源极/漏极区域（6）上方的区域的氧化物 - 氮化物 - 氧化物层序列。

    SEMICONDUCTOR MEMORY DEVICE HAVING CHARGE-TRAPPING MEMORY CELLS
    3.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE HAVING CHARGE-TRAPPING MEMORY CELLS 审中-公开
    具有电荷捕获存储器电池的半导体存储器件

    公开(公告)号：WO2006034854A3

    公开(公告)日：2006-06-22

    申请号：PCT/EP2005010470

    申请日：2005-09-28

    Applicant: INFINEON TECHNOLOGIES AG ,  VERHOEVEN MARTIN

    Inventor： VERHOEVEN MARTIN

    IPC: H01L27/115 ,  G11C16/04 ,  H01L21/336 ,  H01L21/768 ,  H01L21/8247 ,  H01L27/02 ,  H01L29/786 ,  H01L29/788 ,  H01L29/792

    CPC classification number: H01L29/7851 ,  G11C16/0475 ,  H01L21/76895 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/66795 ,  H01L29/66833 ,  H01L29/7887 ,  H01L29/7923

    Abstract: The memory cell is arranged in a ridge (15) of semiconductor material forming a fin (1) with sidewalls and a channel region between source and drain regions (2). Memory layer sequences (4), such as ONO, provided for charge-trapping are applied to the sidewalls, and gate electrodes are arranged on both sides of the ridge. A plurality of ridges at a distance parallel to one another and have sidewalls facing a neighboring ridge form an array of charge-trapping memory cells. Wordlines are arranged between the ridges, sections of the wordlines forming the gate electrodes (3). This arrangement enables a double gate operation of the cells and thus allows for a storage of four bits of information in every single memory cell structure.

    Abstract translation: 存储单元布置在形成具有侧壁和源极和漏极区域（2）之间的沟道区域的鳍片（1）的半导体材料的脊（15）中。 提供用于电荷俘获的存储层序列（4），例如ONO，被施加到侧壁，并且栅电极被布置在脊的两侧。 在彼此平行的距离处并且具有面向相邻脊的侧壁的多个脊形成电荷捕获存储单元的阵列。 字线布置在脊之间，形成栅电极（3）的字线的部分。 这种布置使得能够对单元进行双栅极操作，从而允许在每个单个存储单元结构中存储四位信息。

    4.
    发明专利
    未知

    公开(公告)号：DE102006024735A1

    公开(公告)日：2007-10-18

    申请号：DE102006024735

    申请日：2006-05-26

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： MANGER DIRK ,  BOUBEKEUR HOCINE ,  VERHOEVEN MARTIN ,  NAGEL NICOLAS ,  TATRY THOMAS ,  CASPARY DIRK ,  MARKERT MATTHIAS

    IPC: G03F7/11 ,  G03F7/09 ,  H01L21/033 ,  H01L21/768

    Abstract: A hard mask layer stack for patterning a layer to be patterned includes a carbon layer disposed on top of the layer to be patterned, a first layer of a material selected from the group of SiO2 and SiON disposed on top of the carbon layer and a silicon layer disposed on top of the first layer. A method of patterning a layer to be patterned includes providing the above described hard mask layer stack on the layer to be patterned and patterning the silicon hard mask layer in accordance with a pattern to be formed in the layer that has to be patterned.

    Simple non-volatile resistive memory element includes first material with insulating oxide and second material with conductive oxide
    8.
    发明专利
    Simple non-volatile resistive memory element includes first material with insulating oxide and second material with conductive oxide 未知

    公开(公告)号：DE102004057236A1

    公开(公告)日：2006-06-08

    申请号：DE102004057236

    申请日：2004-11-26

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： VERHOEVEN MARTIN

    IPC: H01L27/24

    Abstract: The following are provided: a material zone (14) with or of electrically-conductive first material (14', M), a second material zone with or of an electrically-conductive second material (18', M) and between and in direct mechanical and electrical contact with this an oxidation material zone (16) with or of an oxidation material (16'), as a memory material zone (S). The oxidation material is an oxidized form of the first material and/or an oxidized form of the second material. The first material is selected for its insulating- (or highly electrically-resistive) oxidized form; the second material is selected for its conductive- (or only slightly electrically-resistive) oxidized form. An independent claim is included for the corresponding method of manufacture.

    10.
    发明专利
    未知

    公开(公告)号：DE102004050641A1

    公开(公告)日：2006-04-06

    申请号：DE102004050641

    申请日：2004-10-18

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： VERHOEVEN MARTIN

    IPC: H01L27/115

    Abstract: The channel region is slightly elevated with respect to the source and drain regions to form steps in the semiconductor surface, which are covered by a dielectric memory layer sequence provided for charge-trapping, the memory layer sequence comprising a lower confinement layer, a memory layer and an upper confinement layer. Electrons that are accelerated from source to drain are more probably scattered on a straight trajectory, on which they pass the lower confinement layer and are trapped in the memory layer. This memory cell aims at improving the speed of write operations.

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