公开(公告)号：DE10123362B4

公开(公告)日：2004-12-30

申请号：DE10123362

申请日：2001-05-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ABDUL-HAK AYAD ,  CASPARY DIRK ,  GRATZ ACHIM ,  HAIBACH PATRICK ,  KAMIENSKI ELARD STEIN VON ,  KUTTER CHRISTOPH

IPC: G01R31/3185 ,  H01L23/544 ,  H01L21/66

公开(公告)号：DE10259783A1

公开(公告)日：2004-07-15

申请号：DE10259783

申请日：2002-12-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PARASCANDOLA STEFANO ,  HABERKERN ROLAND ,  CASPARY DIRK ,  KNOEFLER ROMAN ,  HAUFE JUERG ,  KLEINT CHRISTOPH ,  SCHULZE NORBERT ,  POLEI VERONIKA ,  SACHSE JENS-UWE ,  DEPPE JOACHIM ,  RIEDEL STEPHAN ,  LUDWIG CHRISTOPH ,  HAIBACH PATRICK ,  STEIN VON KAMIENSKI ELARD

IPC: H01L21/8246 ,  H01L27/115 ,  H01L21/8247

Abstract: In first step specified insulation (5) is deposited on semiconductor substrate (1) and onto surface is applied memory layer stack of first boundary layer (2), memory layer (3) and second boundary layer (4). In second step, first conductivity doped troughs (6) are formed by mask technique and application of doping material into semiconductor substrate. In third step, opposite conductivity doped troughs (7) are formed by doping semiconductor substrate. By using the same mask, in second step at least second boundary layer in region (10) for first conductivity troughs is removed. By using the same mask, in third layer at least second boundary layer in region (11) for second conductivity troughs is removed.

公开(公告)号：DE10108924A1

公开(公告)日：2002-09-05

申请号：DE10108924

申请日：2001-02-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ABDUL-HAK AYAD ,  CASPARY DIRK ,  GRATZ ACHIM ,  HAIBACH PATRICK ,  KAMIENSKI ELARD STEIN VON ,  KUTTER CHRISTOPH

IPC: H01L21/66 ,  H01L23/544

公开(公告)号：DE102005040883B3

公开(公告)日：2007-01-04

申请号：DE102005040883

申请日：2005-08-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PARASCANDOLA STEFANO ,  CASPARY DIRK

IPC: H01L21/768 ,  B81C1/00 ,  G03F7/16

Abstract: The method involves applying two spacer layers conformally on a structure layer, and etching the spacer layers anisotropically, so that a spacer (5) is formed on side walls of lamellar portions of the structure layer and a spacer (7) is formed on side walls of the spacer (5).. The structure layer is removed, so that the spacer stays with the respective side walls, and a complementary layer (8) is applied to fill free spaces. An even surface is formed on an upper side of the spacers and the complementary layer, and the two spacers or the complementary layer are removed.

公开(公告)号：DE10206374A1

公开(公告)日：2003-09-04

申请号：DE10206374

申请日：2002-02-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： STEIN VON KAMIENSKI ELARD ,  GAERTNER THOMAS ,  SCHULZE JOERG ,  CASPARY DIRK

IPC: H01L21/265 ,  H01L21/316 ,  H01L21/321 ,  H01L21/768 ,  H01L21/8246

Abstract: Production of planar NROM (nitrided read only memory) cells having gate electrodes, a gate oxide and bit lines comprises forming an oxide for insulating the bit lines and an oxide for forming the gate oxide whilst thermally oxidizing a semiconductor material. Nitrogen is implanted in the region of the bit lines before the oxide of the bit lines is formed in the semiconductor material so that an oxidation rate is adjusted. Preferred Features: Additional low voltage components are produced. Implantation of nitrogen in the region of the bit lines is carried out so that the oxidation rate is lower than the oxidation rate in the region of the components.

公开(公告)号：DE10143722C2

公开(公告)日：2003-07-03

申请号：DE10143722

申请日：2001-08-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： CASPARY DIRK ,  KAULFUSS DORIT

IPC: B07C5/34 ,  B65G49/07 ,  H01L21/00 ,  B65G1/00 ,  H01L21/68

公开(公告)号：DE10123362A1

公开(公告)日：2002-11-28

申请号：DE10123362

申请日：2001-05-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ABDUL-HAK AYAD ,  CASPARY DIRK ,  GRATZ ACHIM ,  HAIBACH PATRICK ,  KAMIENSKI ELARD STEIN VON ,  KUTTER CHRISTOPH

IPC: G01R31/3185 ,  H01L23/544 ,  H01L21/66

Abstract: The device has electronic chips and a memory device with a stored classification map with position and classification information for at least one part of the chip. The position information gives the position of each chip on the wafer and the classification information gives a classification of each chip in accordance with a given criterion. An Independent claim is also included for a wafer manufacturing method.

公开(公告)号：DE102006030015B4

公开(公告)日：2008-03-13

申请号：DE102006030015

申请日：2006-06-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： CASPARY DIRK ,  RIEDEL STEPHAN ,  PARASCANDOLA STEFANO

IPC: H01L21/8247 ,  H01L27/115

Abstract: At least one memory layer is provided on a substrate surface. A plurality of parallel conductor strips is formed from electrically conductive material above the memory layer. Sidewalls of the conductor strips are provided with spacers of an electrically conductive material.

公开(公告)号：DE102006030015A1

公开(公告)日：2007-10-11

申请号：DE102006030015

申请日：2006-06-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： CASPARY DIRK ,  RIEDEL STEPHAN ,  PARASCANDOLA STEFANO

IPC: H01L21/8247 ,  H01L27/115

Abstract: At least one memory layer is provided on a substrate surface. A plurality of parallel conductor strips is formed from electrically conductive material above the memory layer. Sidewalls of the conductor strips are provided with spacers of an electrically conductive material.

公开(公告)号：DE102005048197B3

公开(公告)日：2007-04-26

申请号：DE102005048197

申请日：2005-10-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： OLLIGS DOMINIK ,  MUELLER TORSTEN ,  PARASCANDOLA STEFANO ,  RIEDEL STEPHAN ,  CASPARY DIRK ,  KNOEFLER ROMAN

IPC: H01L27/115 ,  H01L21/8247

Abstract: The bit lines are produced by an implantation of a dopant by means of a sacrificial hard mask layer, which is later replaced with the gate electrodes formed of polysilicon in the memory cell array. Striplike areas of the memory cell array, which run transversely to the bit lines, are reserved by a blocking layer to be occupied by the bit line contacts. In these areas, the hard mask is used to form contact holes, which are self-aligned with the implanted buried bit lines. Between the blocked areas, the word lines are arranged normally to the bit lines.