公开(公告)号：DE102004049356B4

公开(公告)日：2006-06-29

申请号：DE102004049356

申请日：2004-10-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： THOMAS JOCHEN ,  LUDEWIG SYLKE ,  GRAFE JUERGEN ,  WEITZ PETER

IPC: H01L25/065

Abstract: A semiconductor module having an internal semiconductor chip stack on a wiring substrate is disclosed. In one embodiment, the semiconductor chip stack has semiconductor chips which are arranged such that they are offset, the semiconductor chips having bonding connection pads in at least one edge region of their active top side. These bonding connection pads are electrically connected to the wiring substrate via bonding connections. In this case, the semiconductor chips are stacked on top of one another in an offset manner such that the bonding connection pads remain free of a semiconductor chip which is stacked on top of them. In this case, the semiconductor chips may be identical silicon chips which may differ, for example in pairs, in terms of their wiring structure for the centrally arranged contact areas in different edge regions.

公开(公告)号：DE102005015036A1

公开(公告)日：2006-02-16

申请号：DE102005015036

申请日：2005-03-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： REISS MARTIN ,  GRAFE JUERGEN ,  LEGEN ANTON ,  CARMONA MANUEL

IPC: H01L21/58 ,  H01L21/60 ,  H01L23/50

Abstract: An electronic component includes a base and a chip attached to the base by a plurality of adhesive pads that are spaced apart from one another and are arranged in an intermediate space between the chip and the base. The chip is electrically connected to interconnects of the base. The adhesive pads are partitioned in a regular distribution over the entire surface area of the chip. A molding compound surrounds the chip and is disposed in the intermediate space between the chip and the base.

公开(公告)号：DE10339770A1

公开(公告)日：2005-03-31

申请号：DE10339770

申请日：2003-08-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： THOMAS JOCHEN ,  GRAFE JUERGEN ,  WENNEMUTH INGO ,  GOSPODINOVA-DALTCHEVA MINKA ,  KUZMENKA MAKSIM

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/50

Abstract: The FBGA (fine pitch ball grid array) connection device (5) is for face-down integrated circuit chips (6). It has balls of solder (14) acting as electrical contacts on the underside of the chip. The balls are in contact with through-connectors (13) under a copper layer (18) and the chip. The connectors extend through two substrate plates (1,2). A central bonding channel extends through holes in the substrate. It consists of a stepped diameter cast mass of insulating material (16) containing bridging wires (10). The chip is encapsulated in a molding compound (17).

公开(公告)号：DE10339770B4

公开(公告)日：2007-08-30

申请号：DE10339770

申请日：2003-08-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： THOMAS JOCHEN ,  GRAFE JUERGEN ,  WENNEMUTH INGO ,  GOSPODINOVA-DALTCHEVA MINKA ,  KUZMENKA MAKSIM

IPC: H01L23/50 ,  H01L21/60 ,  H01L23/31 ,  H01L23/498

公开(公告)号：DE102005001590A1

公开(公告)日：2006-07-20

申请号：DE102005001590

申请日：2005-01-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： THOMAS JOCHEN ,  BENDER CARSTEN ,  GRAFE JUERGEN ,  WENNEMUTH INGO ,  GOSPODINOVA MINKA ,  SAVIGNAC DOMINIQUE

IPC: H01L23/50 ,  H01L25/065

Abstract: Package has a silicon chip, fixed with its active side to a substrate (12), including a core having copper wires (15.1, 15.2) on both sides. Build-up layers (16.1, 16.2) with copper wire (17.1, 17.2) are found on the copper wires (15.1, 15.2). Build-up layers are structured on ball side by pressure and back etching process, so that the copper wires (17.1, 17.2) on the substrate is directly accessible in canal for wire bonds.

公开(公告)号：DE102005001590B4

公开(公告)日：2007-08-16

申请号：DE102005001590

申请日：2005-01-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： THOMAS JOCHEN ,  BENDER CARSTEN ,  GRAFE JUERGEN ,  WENNEMUTH INGO ,  GOSPODINOVA MINKA ,  SAVIGNAC DOMINIQUE

IPC: H01L23/50 ,  H01L25/065

公开(公告)号：DE102005010156A1

公开(公告)日：2005-10-06

申请号：DE102005010156

申请日：2005-03-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GRAFE JUERGEN ,  HEDLER HARRY ,  POHL JENS ,  THOMAS JOCHEN ,  WEITZ PETER

IPC: G11C5/14 ,  H01L23/48 ,  H01L23/50 ,  H01L25/065

Abstract: An apparatus and a method of manufacture for a stacked-die assembly. A first die is placed on a substrate such that the backside of the die, i.e., the side opposite the side with the bond pads, is coupled to the substrate, preferably by an adhesive. Wire leads electrically couple the bond pads of the first die to contacts on the substrate. A second die is placed on the first die, and wire leads electrically couple the bond pads of the second die to contacts on the substrate. Preferably, a spacer is placed between the first die and the second die. Additional dies may be stacked on the second die.

公开(公告)号：DE102004049356A1

公开(公告)日：2006-04-20

申请号：DE102004049356

申请日：2004-10-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： THOMAS JOCHEN ,  LUDEWIG SYLKE ,  GRAFE JUERGEN ,  WEITZ PETER

IPC: H01L25/065

Abstract: A semiconductor module having an internal semiconductor chip stack on a wiring substrate is disclosed. In one embodiment, the semiconductor chip stack has semiconductor chips which are arranged such that they are offset, the semiconductor chips having bonding connection pads in at least one edge region of their active top side. These bonding connection pads are electrically connected to the wiring substrate via bonding connections. In this case, the semiconductor chips are stacked on top of one another in an offset manner such that the bonding connection pads remain free of a semiconductor chip which is stacked on top of them. In this case, the semiconductor chips may be identical silicon chips which may differ, for example in pairs, in terms of their wiring structure for the centrally arranged contact areas in different edge regions.

公开(公告)号：DE19612713B4

公开(公告)日：2005-08-18

申请号：DE19612713

申请日：1996-03-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HAUEIS NORBERT ,  EIGENSTETTER PETER ,  LEITMEIR MANFRED ,  GRAFE JUERGEN

IPC: G01R31/28 ,  H05K13/00 ,  G01R31/26 ,  B07C5/00 ,  B07C5/344 ,  B65B5/00 ,  H01L21/66