公开(公告)号：WO2005081316A3

公开(公告)日：2006-01-12

申请号：PCT/DE2005000302

申请日：2005-02-22

Applicant: INFINEON TECHNOLOGIES AG ,  HETZEL WOLFGANG ,  THOMAS JOCHEN ,  WEITZ PETER ,  WENNEMUTH INGO

Inventor： HETZEL WOLFGANG ,  THOMAS JOCHEN ,  WEITZ PETER ,  WENNEMUTH INGO

IPC: H01L23/31 ,  H01L25/065 ,  H01L25/10

CPC classification number: H01L23/3128 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The invention relates to a semiconductor component (10) comprising an interposer substrate (1) and provided in the form of a stack element of a semiconductor component stack (25). The interposer substrate (1) comprises, on one of the interposer substrate sides (2, 4), a semiconductor chip that is protected in its lateral edges (22) by a plastic compound (12). An interposer structure (3) is placed on the interposer side (2, 4) opposite the semiconductor chip (6) and is partially covered by a plastic compound (12). Edge areas (11) of the interposer substrate (1) remain free from any plastic compound (12) and have, on both interposer sides (2, 4), outer lands (7) which are connected to one another by via holes (8).

Abstract translation: 本发明涉及具有内插基板（1）作为半导体元件堆（25）的堆叠元件的半导体器件（10）。 内插基板（1）具有半导体芯片，其通过塑性体（12）在其侧边缘（22）保护的Umverdrahtungssubstratseiten（2,4）中的一个。 设置在半导体芯片（6）Umverdrahtungsseite相对上（2,4）是一个再布线结构（3），其部分地由塑性体（12）覆盖。 内插基板（1）的边缘部分（11）保持自由的任何塑料材料（12）的和具有两个Umverdrahtungsseiten（2,4）的外部接触垫（7），其经由通过触点电连接（8）。

公开(公告)号：WO2005022588A2

公开(公告)日：2005-03-10

申请号：PCT/DE2004001853

申请日：2004-08-19

Applicant: INFINEON TECHNOLOGIES AG ,  GOSPODINOVA-DALTCHEVA MINKA ,  HUEBERT HARRY ,  SUBRAYA RAJESH ,  THOMAS JOCHEN ,  WENNEMUTH INGO

Inventor： GOSPODINOVA-DALTCHEVA MINKA ,  HUEBERT HARRY ,  SUBRAYA RAJESH ,  THOMAS JOCHEN ,  WENNEMUTH INGO

IPC: H01L23/13 ,  H01L23/31 ,  H01L23/49 ,  H01L23/498 ,  H01L23/50 ,  H01L23/552 ,  H01L23/66 ,  H01L25/065 ,  H01L

CPC classification number: H01L25/0657 ,  H01L23/13 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/552 ,  H01L23/66 ,  H01L24/33 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2223/6627 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/49 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06575 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/0101 ,  H01L2924/01013 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01052 ,  H01L2924/01068 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/1903 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: The invention relates to a semiconductor component comprising a plastic housing (41), at least one semiconductor chip (1), and a rewiring layer (8). The rewiring layer (8) is provided with an insulating level (9) and a rewiring level (10). The rewiring level (10) encompasses alternately disposed parallel signal conductors (12) and ground or power supply conductors (13) or exclusively parallel signal conductors (12). In the latter case, a electrically conducting metallic layer that can be connected to ground potential or power supply potential is additionally provided to close the rewiring layer or in the form of a coating.

Abstract translation: 本发明涉及一种具有塑料外壳（41），至少一个半导体芯片（1）和重新布线层（8）的半导体器件。 再布线层（8）具有绝缘层（9）和再布线层（10）。 重新布线层（10）彼此平行并且交替地布置信号导体迹线（12）和接地或供电导体迹线（13）或者仅彼此平行布置的信号导体迹线（12）。 在后一种情况下，可以连接到接地或供电电位的导电金属层作为再布线层的终端或以覆盖层的形式额外提供。

公开(公告)号：WO2005045926A3

公开(公告)日：2005-09-09

申请号：PCT/DE2004002374

申请日：2004-10-25

Applicant: INFINEON TECHNOLOGIES AG ,  HETZEL WOLFGANG ,  THOMAS JOCHEN

Inventor： HETZEL WOLFGANG ,  THOMAS JOCHEN

IPC: H01L23/00 ,  H01L23/31

CPC classification number: H01L23/562 ,  H01L23/3114 ,  H01L23/3128 ,  H01L24/48 ,  H01L2224/32225 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The invention relates to a semiconductor component (1) comprising a synthetic housing material (2), a semiconductor chip (3) and a circuit support (4). The semiconductor chip (3) is embedded in the synthetic housing material (2). The top surface of the semiconductor chip (3) and the synthetic housing material (2) are disposed on a circuit support (4). An elastic adhesive layer (11) is interposed between the circuit support (4) and the synthetic housing material (2) comprising the semiconductor chip (3), thereby mechanically decoupling an upper area from a lower area of the semiconductor component (1).

Abstract translation: 本发明涉及一种半导体元件（1）与塑料封装模塑料（2），半导体芯片（3）以及在电路载体（5）。 半导体芯片（3）被嵌入在塑料封装成型化合物（2）。 半导体芯片（3）和所述塑料封装成型化合物（2）的顶表面被布置在电路载体（4）上。 电路载体（4）和所述塑料封装成型化合物（2）与所述半导体芯片之间（3）是用于半导体器件的下部区域的顶部的机械去耦的弹性粘接剂层（11）（1）。

公开(公告)号：DE10339770A1

公开(公告)日：2005-03-31

申请号：DE10339770

申请日：2003-08-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： THOMAS JOCHEN ,  GRAFE JUERGEN ,  WENNEMUTH INGO ,  GOSPODINOVA-DALTCHEVA MINKA ,  KUZMENKA MAKSIM

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/50

Abstract: The FBGA (fine pitch ball grid array) connection device (5) is for face-down integrated circuit chips (6). It has balls of solder (14) acting as electrical contacts on the underside of the chip. The balls are in contact with through-connectors (13) under a copper layer (18) and the chip. The connectors extend through two substrate plates (1,2). A central bonding channel extends through holes in the substrate. It consists of a stepped diameter cast mass of insulating material (16) containing bridging wires (10). The chip is encapsulated in a molding compound (17).

公开(公告)号：DE10255289A1

公开(公告)日：2004-06-17

申请号：DE10255289

申请日：2002-11-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： THOMAS JOCHEN ,  HETZEL WOLFGANG

IPC: H01L23/495 ,  H01L23/50 ,  H01L25/065 ,  H01L21/50

Abstract: An electronic component has a chip stack with a first semiconductor chip, a second semiconductor chip, and a large number of flat conductors configured in between the first semiconductor chip and the a second semiconductor chip. The flat conductors have a central section on which the semiconductor chips are mounted. First bonding connections connect the first semiconductor chip to inner sections of the flat conductors. Second bonding connections connect the second semiconductor chip to transitional sections of the flat conductors. The outer sections of the flat conductors project out of a package.

公开(公告)号：DE102004049356B4

公开(公告)日：2006-06-29

申请号：DE102004049356

申请日：2004-10-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： THOMAS JOCHEN ,  LUDEWIG SYLKE ,  GRAFE JUERGEN ,  WEITZ PETER

IPC: H01L25/065

Abstract: A semiconductor module having an internal semiconductor chip stack on a wiring substrate is disclosed. In one embodiment, the semiconductor chip stack has semiconductor chips which are arranged such that they are offset, the semiconductor chips having bonding connection pads in at least one edge region of their active top side. These bonding connection pads are electrically connected to the wiring substrate via bonding connections. In this case, the semiconductor chips are stacked on top of one another in an offset manner such that the bonding connection pads remain free of a semiconductor chip which is stacked on top of them. In this case, the semiconductor chips may be identical silicon chips which may differ, for example in pairs, in terms of their wiring structure for the centrally arranged contact areas in different edge regions.

公开(公告)号：DE102004038989A1

公开(公告)日：2005-12-29

申请号：DE102004038989

申请日：2004-08-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOSPODINOVA-DALTCHEVA MINKA ,  THOMAS JOCHEN ,  IRSIGLER ROLAND

IPC: H01L25/065 ,  H01L27/108

Abstract: The module has an inner semiconductor chip stack (2) that exhibits an upper semiconductor chip and a lower semiconductor chip (4). The lower semiconductor chip exhibits a back wiring structure on its back. The lower semiconductor chip is electrically connected with flip chip contacts of the upper semiconductor chip. The back wiring structure stands over bond connections with external contacts of wiring substrates that are connected. An independent claim is also included for a method for manufacturing a semiconductor module.

公开(公告)号：DE10259221A1

公开(公告)日：2004-07-15

申请号：DE10259221

申请日：2002-12-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： THOMAS JOCHEN ,  HETZEL WOLFGANG ,  LEGEN ANTON

IPC: H01L23/31 ,  H01L25/065 ,  H01L23/50 ,  H01L21/50

Abstract: An electronic component comprises a semiconductor chip stack (3,4) on a wiring substrate (11) having external contacts (12). Between the chips is a wiring layer (7) having a through opening (8) and contact regions (9,10). Connections are made through the opening and there is a plastic housing (18,19) for the component. An Independent claim is also included for a production process for the above.

公开(公告)号：DE102005039786A1

公开(公告)日：2007-03-15

申请号：DE102005039786

申请日：2005-08-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： THOMAS JOCHEN ,  HETZEL WOLFGANG

IPC: H01L23/50

Abstract: Dual-die ball grid array (DDBGA) (30) comprises copper wiring planes on a multiplanar substrate (33) with stacked dies with opposite ball pads to receive solder balls (37) that are electrically connected to bond pads on the dies. The electrical leads to connect the lower dies (35) to the ball pads of the ball grid array substrate are lengthened to correspond with the length of the upper die (46) connections in which chip signals of the lower dies are led around from the form the wire bridges (32) through vias (41) in the substrate on to additional leads (42).

公开(公告)号：DE102004049356A1

公开(公告)日：2006-04-20

申请号：DE102004049356

申请日：2004-10-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： THOMAS JOCHEN ,  LUDEWIG SYLKE ,  GRAFE JUERGEN ,  WEITZ PETER

IPC: H01L25/065

Abstract: A semiconductor module having an internal semiconductor chip stack on a wiring substrate is disclosed. In one embodiment, the semiconductor chip stack has semiconductor chips which are arranged such that they are offset, the semiconductor chips having bonding connection pads in at least one edge region of their active top side. These bonding connection pads are electrically connected to the wiring substrate via bonding connections. In this case, the semiconductor chips are stacked on top of one another in an offset manner such that the bonding connection pads remain free of a semiconductor chip which is stacked on top of them. In this case, the semiconductor chips may be identical silicon chips which may differ, for example in pairs, in terms of their wiring structure for the centrally arranged contact areas in different edge regions.