-
公开(公告)号:DE102005046404B4
公开(公告)日:2008-12-24
申请号:DE102005046404
申请日:2005-09-28
Applicant: INFINEON TECHNOLOGIES AG
Inventor: BORGHOFF GEORG , NUEBEL THOMAS , SPANKE REINHOLD , WOELZ MARTIN
Abstract: The method involves rolling the metal base plates (4) in a preferential direction such as its longitudinal direction. The base plates can be made from copper or aluminium. Independent claim describes semi conductor module with semi conductor component (2) mounted on a base plate (4) which is rolled in its longitudinal direction.
-
公开(公告)号:DE102006034599A1
公开(公告)日:2008-01-31
申请号:DE102006034599
申请日:2006-07-26
Applicant: INFINEON TECHNOLOGIES AG
Inventor: WEIS BENNO , PETERS DETHARD , WOELZ MARTIN
Abstract: The method involves preparing a wafer (10), which is rotated around a rotation axis (R) during manufacturing or processing and has many unscattered semiconductor chips and successively arranging many grouping zones (21 to 24) in radial direction to which each section of the wafer is assigned. Each semiconductor chip of the wafer is partly assigned in the grouping areas, where two semiconductor chips, which are assigned to grouping zones, are connected. An independent claim is also included for a method for interconnecting semiconductor chips, which are manufactured on a common wafer.
-
公开(公告)号:DE102005046404A1
公开(公告)日:2007-04-05
申请号:DE102005046404
申请日:2005-09-28
Applicant: INFINEON TECHNOLOGIES AG
Inventor: BORGHOFF GEORG , NUEBEL THOMAS , SPANKE REINHOLD , WOELZ MARTIN
Abstract: The method involves rolling the metal base plates (4) in a preferential direction such as its longitudinal direction. The base plates can be made from copper or aluminium. Independent claim describes semi conductor module with semi conductor component (2) mounted on a base plate (4) which is rolled in its longitudinal direction.
-
公开(公告)号:DE102006034599B4
公开(公告)日:2010-01-21
申请号:DE102006034599
申请日:2006-07-26
Applicant: INFINEON TECHNOLOGIES AG
Inventor: WEIS BENNO , PETERS DETHARD , WOELZ MARTIN
IPC: H01L21/77 , H01L21/60 , H01L23/544
Abstract: The method involves preparing a wafer (10), which is rotated around a rotation axis (R) during manufacturing or processing and has many unscattered semiconductor chips and successively arranging many grouping zones (21 to 24) in radial direction to which each section of the wafer is assigned. Each semiconductor chip of the wafer is partly assigned in the grouping areas, where two semiconductor chips, which are assigned to grouping zones, are connected. An independent claim is also included for a method for interconnecting semiconductor chips, which are manufactured on a common wafer.
-
公开(公告)号:DE102006004031B3
公开(公告)日:2007-03-08
申请号:DE102006004031
申请日:2006-01-27
Applicant: INFINEON TECHNOLOGIES AG
Inventor: SCHILLING OLIVER , WOELZ MARTIN
IPC: H01L25/07 , H01L23/498 , H02M1/00
Abstract: At least four substrates (41-44) are arranged in a row on a carrier board (40). Components (414,415) on each individual substrate are connected to form an electrical half-bridge. For each individual substrate, the sequence of connection points for the low and high potentials corresponds exactly to a sequence of external connection terminals (10,20) on two bus rails (1,2) in the direction of the row of substrates.
-
-
-
-