公开(公告)号：JP2007019515A

公开(公告)日：2007-01-25

申请号：JP2006187597

申请日：2006-07-07

Applicant: Infineon Technologies Ag ,  インフィネオン テクノロジーズ アクチエンゲゼルシャフト

Inventor： HIELEMANN MATTHIAS ,  LIAN JINGYU ,  STIERSTORFER RUDOLF

IPC: H01L21/8238 ,  H01L21/76 ,  H01L21/762 ,  H01L27/08 ,  H01L27/092 ,  H01L29/786 ,  H01L41/08 ,  H01L41/18

CPC classification number: H01L21/84 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/517 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/7849

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device in which mobility of carriers in a transistor can be improved.
SOLUTION: The semiconductor device 100 is provided with an n-channel transistor 118 arranged on a semiconductor substrate, a p-channel transistor 116 arranged on the semiconductor substrate, and a piezoelectric liner 110 adjacent to the n-channel transistor 118 and the p-channel transistor 116.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供可以提高晶体管中载流子迁移率的半导体器件。 解决方案：半导体器件100设置有布置在半导体衬底上的n沟道晶体管118，布置在半导体衬底上的p沟道晶体管116和与n沟道晶体管118相邻的压电衬垫110，以及 p沟道晶体管116.（C）2007，JPO＆INPIT

公开(公告)号：JP2008096973A

公开(公告)日：2008-04-24

申请号：JP2007211402

申请日：2007-08-14

Applicant: Infineon Technologies Ag ,  インフィネオン テクノロジーズ アクチエンゲゼルシャフト

Inventor： LIAN JINGYU ,  LIPINSKY MATTHIAS ,  SARMA CHANDRASEKHAR ,  ZHUANG HAOREN

IPC: G03F1/08 ,  H01L21/027

CPC classification number: G03F7/70425 ,  G03F7/70483

Abstract: PROBLEM TO BE SOLVED: To provide: a measurement system by which corner rounding is reduced; a measurement method; an alteration of a mask; and a lithography process. SOLUTION: A method of manufacturing a semiconductor device includes providing a mask having a plurality of corner rounding test patterns formed thereon. A layer of photosensitive material of a first semiconductor device is patterned with a plurality of corner rounding test features using the mask and a lithography process. An amount of the corner rounding of the lithography process is measured by analyzing the plurality of corner rounding test features formed on the layer of photosensitive material of the semiconductor device, compared with a plurality of other corner rounding test features. The lithography process or the mask is altered in response to the amount of corner rounding measured, and a second semiconductor device is provided. The second semiconductor device is processed using the altered lithography process or the altered mask. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供：减少角落圆度的测量系统; 测量方法; 改变面具; 和光刻工艺。 解决方案：制造半导体器件的方法包括提供具有形成在其上的多个角圆形测试图案的掩模。 使用掩模和光刻工艺，利用多个拐角圆形测试特征对第一半导体器件的感光材料层进行构图。 通过分析形成在半导体器件的感光材料层上的多个拐角圆形测试特征，与多个其他圆角圆形测试特征相比，测量光刻工艺的角圆角的量。 光刻处理或掩模响应于测量的角圆度的量而改变，并且提供第二半导体器件。 使用改变的光刻工艺或改变的掩模来处理第二半导体器件。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2009004795A

公开(公告)日：2009-01-08

申请号：JP2008182052

申请日：2008-07-11

Applicant: Infineon Technologies Ag ,  インフィネオン テクノロジーズ アクチエンゲゼルシャフト

Inventor： LIAN JINGYU

IPC: H01L21/822 ,  H01L21/00 ,  H01L21/02 ,  H01L21/768 ,  H01L21/8246 ,  H01L27/04 ,  H01L29/76

CPC classification number: H01L28/55 ,  H01L21/76897 ,  H01L27/11507

Abstract: PROBLEM TO BE SOLVED: To provide a method for inhibiting plug oxidation during the manufacturing of a capacitor.
SOLUTION: A ferroelectric capacitor device is provided with a substrate 5, a plug 4 passing through the substrate 5, an electrically insulating layer 6 formed on the substrate 5, a first electrode 8 formed on the electrically insulating layer 6, a ferroelectric layer 10 formed on the first electrode 8, and a second electrode 12 formed on the ferroelectric layer 10. The first electrode 8 is electrically connected to the plug 4 through the electrically insulating layer 6 and an inter-layer insulating film 34 is formed on the electrical connection portion.
COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供一种在制造电容器期间抑制塞子氧化的方法。 解决方案：铁电电容器装置设置有基板5，穿过基板5的塞子4，形成在基板5上的电绝缘层6，形成在电绝缘层6上的第一电极8，铁电体 形成在第一电极8上的层10和形成在铁电层10上的第二电极12.第一电极8通过电绝缘层6电连接到插塞4，并且在第一电极8上形成层间绝缘膜34 电连接部分。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：DE10243468A1

公开(公告)日：2003-05-15

申请号：DE10243468

申请日：2002-09-19

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： LIAN JINGYU ,  LIN CHENTING ,  SAENGER KATHERINE ,  WONG KWONG HON

IPC: C23C16/40 ,  C23C16/56 ,  H01L21/02 ,  H01L21/314 ,  H01L21/316 ,  H01L21/3105 ,  H01L21/8239

Abstract: A method for forming a crystalline dielectric layer deposits an amorphous metallic oxide dielectric layer on a surface. The amorphous metallic oxide dielectric layer is treated with a plasma at a temperature of less than or equal to 400 degrees Celsius to form a crystalline layer.

公开(公告)号：WO2004068539A3

公开(公告)日：2005-02-10

申请号：PCT/SG2004000018

申请日：2004-01-19

Applicant: INFINEON TECHNOLOGIES AG ,  TOSHIBA KK ,  ZHUANG HAOREN ,  EGGER ULRICH ,  TOMIOKA KAZUHIRO ,  LIAN JINGYU ,  NAGEL NICOLAS ,  HILLIGER ANDREAS ,  BEITEL GERHARD

Inventor： ZHUANG HAOREN ,  EGGER ULRICH ,  TOMIOKA KAZUHIRO ,  LIAN JINGYU ,  NAGEL NICOLAS ,  HILLIGER ANDREAS ,  BEITEL GERHARD

IPC: H01L20060101 ,  H01L21/02 ,  H01L21/311 ,  H01L21/8246 ,  H05K5/00

CPC classification number: H01L28/55 ,  H01L21/31116 ,  H01L28/57

Abstract: The present invention provides a sidewall oxygen diffusion barrier and method for fabricating the sidewall oxygen diffusion barrier to reduce the diffusion of oxygen to contact plugs during CW hole reactive ion etch processing of a ferroelectric capacitor of an FeRAM device. In one embodiment the sidewall barrier is formed from a substrate fence, while in another embodiment the sidewall barrier is formed by etching back an oxygen barrier.

Abstract translation: 本发明提供一种侧壁氧扩散阻挡层和用于制造侧壁氧扩散阻挡层的方法，以在FeRAM器件的铁电电容器的CW孔反应离子蚀刻处理期间减少氧气对接触插塞的扩散。 在一个实施例中，侧壁屏障由衬底栅栏形成，而在另一个实施例中，通过蚀刻回氧屏障来形成侧壁屏障。

公开(公告)号：WO2004059728A2

公开(公告)日：2004-07-15

申请号：PCT/EP0314415

申请日：2003-12-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRUCHHAUS RAINER ,  GERNHARDT STEFAN ,  HILLIGER ANDREAS ,  LIAN JINGYU ,  NAGEL NICOLAS ,  WELLHAUSEN UWE

IPC: H01L21/8246 ,  H01L23/00 ,  H01L21/02 ,  H01L21/8239 ,  H01L27/105

CPC classification number: H01L27/11502 ,  H01L23/562 ,  H01L27/11507 ,  H01L27/1159 ,  H01L29/7842 ,  H01L2924/0002 ,  H01L2924/3511 ,  H01L2924/00

Abstract: A semiconductor chip in which stress on the effective stress on the substrate is reduced in order to reduce bowing. To reduce the effective stress, a stress compensation layer is provided on the backside of the chip. The stress compensating layer produces a stress opposite of that produced by the IC. Thus the overall or effective stress on the substrate is reduced.

Abstract translation: 为了减少弯曲，半导体芯片减小了对基板上的有效应力的应力。 为了降低有效应力，在芯片的背面设置应力补偿层。 应力补偿层产生与IC产生的应力相反的应力。 因此，降低了基板上的整体或有效应力。

公开(公告)号：DE102007011248B4

公开(公告)日：2016-05-19

申请号：DE102007011248

申请日：2007-03-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GUTMANN ALOIS ,  LIAN JINGYU ,  LIPINSKI MATTHIAS ,  SARMA CHANDRASEKHAR ,  ZHUANG HAOREN

IPC: H01L21/66 ,  G06F19/00

Abstract: Eine Prozesssteuermethode, umfassend: Beeinflussen eines ersten Halbleitererzeugnisses (220), verwendend einen ersten Prozess (202); Messen (204) einer Wirkung des ersten Prozesses (202) auf dem ersten Halbleitererzeugnis (220); Beeinflussen des ersten Halbleitererzeugnisses (220), verwendend mindestens einen zweiten Prozess (206); Messen (208) einer Wirkung des mindestens einen zweiten Prozesses (204) auf dem ersten Halbleitererzeugnis (220); Vorwärtskoppeln (270) und Rückkoppeln (262, 272) der auf dem ersten Halbleitererzeugnis (220) gemessenen Wirkung des ersten Prozesses (202) und Rückkoppeln (266b, 266a) der auf dem ersten Halbleitererzeugnis (220) gemessenen Wirkung des mindestens einen zweiten Prozesses (206); Verändern des ersten Prozesses (202), des mindestens einen zweiten Prozesses (206), oder sowohl des ersten Prozesses (202) als auch des mindestens einen zweiten Prozesses (206), basierend auf den vorwärtsgekoppelten (270) und rückgekoppelten (262, 272) gemessenen Wirkungen des ersten Prozesses (202) und den rückgekoppelten (266b, 266a) gemessenen Wirkungen des mindestens einen zweiten Prozesses (206); und Beeinflussen eines zweiten Halbleitererzeugnisses, verwendend den veränderten ersten Prozess (202) und/oder den veränderten mindestens einen zweiten Prozess (206), worin das zweite Halbleitererzeugnis weniger Wafer-zu-Wafer- und Rohchip-zu-Rohchip-Variationen hat in kritischen Abmessungen der Merkmale als das erste Halbleitererzeugnis (220), worin der erste Prozess (202) einen Lithografieprozess umfasst, und worin der mindestens eine zweite Prozess (206) einen Ätzprozess umfasst, worin Verändern des ersten Prozesses (202) umfasst, Reduzieren von Rohchip-zu-Rohchip-Variationen, und worin Verändern des zweiten Prozesses (206) umfasst, Reduzieren von Wafer-zu-Wafer-Variationen, worin der erste Prozess (202) umfasst sequenzielles Bestrahlen einer Vielzahl von Abschnitten des ersten Halbleitererzeugnisses, worin Verändern des ersten Prozesses (202) umfasst, Verändern eines Bestrahlungsprozesses für einen ersten Abschnitt des zweiten Halbleitererzeugnisses, aber nicht Verändern eines Bestrahlungsprozesses für einen zweiten Abschnitt des zweiten Halbleitererzeugnisses.

公开(公告)号：DE112004001788T5

公开(公告)日：2006-07-20

申请号：DE112004001788

申请日：2004-08-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LIAN JINGYU ,  EGGER ULRICH ,  ZHUANG HAOREN

IPC: H01L21/02 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/8246 ,  H01L27/115

Abstract: A method for fabricating a device and a device, such as a ferroelectric capacitor, having a substrate, a contact plug through the substrate, a first barrier layer on the substrate, a first electrode on the first barrier layer, a dielectric layer on the first electrode, and a second electrode on the dielectric layer, comprises etching the second electrode and the dielectric layer of the device using a first hardmask, to shape the second electrode and the dielectric layer. The first hardmask is then removed and one or more encapsulating layers are applied to the second electrode and the dielectric layer. A further hardmask is applied to the one or more encapsulating layers. The first electrode is then etched according to the second hardmask down to the first barrier layer and the second hardmask is then removed from the one or more encapsulating layers.

公开(公告)号：DE112004001438T5

公开(公告)日：2006-07-20

申请号：DE112004001438

申请日：2004-07-06

Applicant: INFINEON TECHNOLOGIES AG ,  TOSHIBA KK

Inventor： ZHUANG HAOREN ,  EGGER ULRICH ,  LIAN JINGYU ,  GERNHARDT STEFAN ,  KANAYA HIROYUKI

IPC: H01L21/20 ,  H01L21/02 ,  H01L21/8246 ,  H01L27/115

公开(公告)号：DE102004009562A1

公开(公告)日：2004-09-16

申请号：DE102004009562

申请日：2004-02-25

Applicant: INFINEON TECHNOLOGIES AG ,  TOSHIBA KK

Inventor： WELLHAUSEN UWE ,  BRUCHHAUS RAINER ,  ZHUANG HAOREN ,  EGGER ULLRICH ,  HORNIK KARL ,  LIAN JINGYU ,  BEITEL GERHARD ,  TOMIOKA KAZUHIRO ,  NATORI KATSUAKI

IPC: H01L21/02 ,  H01L21/033 ,  H01L21/311 ,  H01L21/316 ,  H01L21/3213 ,  H01L21/8246 ,  H01L21/8239

Abstract: In semiconductor device fabrication processes which include the formation of hardmask elements 17 including Al2O2, unwanted Al2O3 is left between the hardmask elements 17. The unwanted Al2O3 includes a layer 9 of Al2O3which is not homogenous across the surface of the structure 3 it overlies, and Al2O3 deposits on the sides of the hardmask elements 17. A method is proposed in which any such unwanted Al2O3 between the hardmask elements 17 is removed by a wet etching step in which the unwanted Al2O3 is exposed to an etchant liquid which etches the Al2O3 at a faster rate than other portions of the structure. This step allows the unwanted Al2O3 to be removed substantially completely without causing significant detriment to those other portions of the structure. Subsequently, an RIE etching step can be performed using the hardmask elements 17 as a mask, without the unwanted Al2O3 obstructing the RIE etching step.